Download presentation

Presentation is loading. Please wait.

1
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 6: Logic/Shift Instructions Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by Ryan Kastner at UCSB and Marry Jane Irwin from PSU

2
Logic and Shift Instructions ECE 15B Spring 2010

3
Bitwise operations Up until now, instructions have been: – Arithmetic (e.g. add, sub, addi) – Memory access (e.g. lw, sw) – Branches and jumps (e.g. j, beq, bne) All these instructions view contents of registers as a single quantity (such as signed or unsigned integer) New Perspective – View contents of register as 32 individual bits rather than as a single 32 bit number – Introduce two new classes of instructions: Logical operations Shift Instructions ECE 15B Spring 2010

4
Logical Operations Instructions for bitwise manipulation OperationCJavaMIPS Shift left<< sll Shift right>>>>> srl Bitwise AND&& and, andi Bitwise OR|| or, ori Bitwise NOT~~ nor Useful for extracting and inserting groups of bits in a word ECE 15B Spring 2010

5
AND Operations Useful to mask bits in a word – Select some bits, clear others to 0 and $t0, $t1, $t2 0000 0000 0000 0000 0000 1101 1100 0000 0000 0000 0000 0000 0011 1100 0000 0000 $t2 $t1 0000 0000 0000 0000 0000 1100 0000 0000 $t0 ECE 15B Spring 2010

6
OR Operations Useful to include bits in a word – Set some bits to 1, leave others unchanged or $t0, $t1, $t2 0000 0000 0000 0000 0000 1101 1100 0000 0000 0000 0000 0000 0011 1100 0000 0000 $t2 $t1 0000 0000 0000 0000 0011 1101 1100 0000 $t0 ECE 15B Spring 2010

7
NOT Operations Useful to invert bits in a word – Change 0 to 1, and 1 to 0 MIPS has NOR 3-operand instruction – a NOR b == NOT ( a OR b ) nor $t0, $t1, $zero 0000 0000 0000 0000 0011 1100 0000 0000 $t1 1111 1111 1111 1111 1100 0011 1111 1111 $t0 Register 0: always read as zero ECE 15B Spring 2010

8
Shift Operations shamt: how many positions to shift Shift left logical (SLL) – Shift left and fill with 0 bits – sll by i bits multiplies by 2 i Shift right logical (SRL) – Shift right and fill with 0 bits – srl by i bits divides by 2 i (unsigned only) Shift right arithmetic (SRA) – Shift right and fill emptied bits by sign extending Note that shamt (immediate value) is only 5 bits oprsrtrdshamtfunct 6 bits 5 bits ECE 15B Spring 2010

9
Uses for Shift Instructions Very convenient operation to extract group of bits (e.g. one byte) within a word (e.g. think of operations on 8-bit pixels or 8-bit characters) For example, suppose we want to get bits 8 to 15 from $t0. The code below will do the job sll $t0, $t0, 16 srl $t0, $t0, 24 ECE 15B Spring 2010

10
Uses for Shift Instructions Since shifting is faster than multiplication, a good compiler (or a good programmer for that matter) usually notices when C code multiplies by a power of 2 and compiles it to a shift instruction For example: a = a*8; (in C) would compile to: sll $s0, $s0, 3 (in MIPS) ECE 15B Spring 2010

11
Overflow when adding and subtracting numbers ECE 15B Spring 2010

12
Integer Addition Example: 7 + 6 Overflow if result out of range Adding +ve and –ve operands, no overflow Adding two +ve operands Overflow if result sign is 1 Adding two –ve operands Overflow if result sign is 0 ECE 15B Spring 2010

13
Integer Subtraction Add negation of second operand Example: 7 – 6 = 7 + (–6) +7:0000 0000 … 0000 0111 –6:1111 1111 … 1111 1010 +1:0000 0000 … 0000 0001 Overflow if result out of range – Subtracting two +ve or two –ve operands, no overflow – Subtracting +ve from –ve operand Overflow if result sign is 0 – Subtracting –ve from +ve operand Overflow if result sign is 1 ECE 15B Spring 2010

14
Dealing with Overflow Some languages (e.g., C) ignore overflow MIPS solution is 2 kinds of arithmetic instructions to recognize 2 choices – add (add), add immediate (addi) and subtract (sub) cause overflow to be detected assuming operation on two’s compliment – add unsigned (addu), add immediate unsigned (addiu) and subtract unsigned (subu) do not cause overflow detection MIPS signals overflow with an exception (aka interrupt) – an unscheduled procedure call where the EPC contains the address of the instruction that caused the exception ECE 15B Spring 2010

15
Multiplication and Division Review ECE 15B Spring 2010

16
Multiply Binary multiplication is just a bunch of right shifts and adds multiplicand multiplier partial product array double precision product n 2n n can be formed in parallel and added in parallel for faster multiplication ECE 15B Spring 2010

17
Multiplication Start with long-multiplication approach 1000 × 1001 1000 0000 1000 1001000 Length of product is the sum of operand lengths multiplicand multiplier product ECE 15B Spring 2010

18
Multiplication Hardware Initially 0 ECE 15B Spring 2010

19
Optimized Multiplier Hardware multiplicand 32-bit ALU multiplier Control add shift right product ECE 15B Spring 2010

20
Optimized Multiplier Hardware: Example multiplicand 32-bit ALU multiplier Control add shift right product 0 1 1 0 = 6 0 0 0 0 0 1 0 1 = 5 add 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 add 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 add 0 1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 add 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 = 30 ECE 15B Spring 2010

21
Faster Multiplier Uses multiple adders – Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel ECE 15B Spring 2010

22
MIPS Multiplication Two 32-bit registers for product – HI: most-significant 32 bits – LO: least-significant 32-bits Instructions – mult rs, rt / multu rs, rt 64-bit product in HI/LO – mfhi rd / mflo rd Move from HI/LO to rd Can test HI value to see if product overflows 32 bits – mul rd, rs, rt Least-significant 32 bits of product –> rd ECE 15B Spring 2010

23
Division Division is just a bunch of quotient digit guesses and left shifts and subtracts dividend = quotient x divisor + remainder dividend divisor partial remainder array quotient n n remainder n 000 0 0 0 ECE 15B Spring 2010

24
Division Check for 0 divisor Long division approach – If divisor ≤ dividend bits 1 bit in quotient, subtract – Otherwise 0 bit in quotient, bring down next dividend bit Restoring division – Do the subtract, and if remainder goes < 0, add divisor back Signed division – Divide using absolute values – Adjust sign of quotient and remainder as required 1001 1000 1001010 -1000 10 101 1010 -1000 10 n-bit operands yield n-bit quotient and remainder quotient dividend remainder divisor ECE 15B Spring 2010

25
Division Hardware Initially dividend Initially divisor in left half ECE 15B Spring 2010

26
Optimized Division Hardware divisor 32-bit ALU quotient Control subtract shift left dividend remainder ECE 15B Spring 2010

27
Optimized Division Hardware divisor 32-bit ALU quotient Control subtract shift left dividend remainder 0 0 1 0 = 2 0 0 0 0 0 1 1 0 = 6 0 0 0 0 1 1 0 0 sub 1 1 1 0 1 1 0 0rem neg, so ‘ient bit = 0 0 0 0 0 1 1 0 0restore remainder 0 0 0 1 1 0 0 0 sub 1 1 1 1 1 1 0 0rem neg, so ‘ient bit = 0 0 0 0 1 1 0 0 0restore remainder 0 0 1 1 0 0 0 0 sub 0 0 0 1 0 0 0 1 rem pos, so ‘ient bit = 1 0 0 1 0 sub 0 0 0 0 0 0 1 1 rem pos, so ‘ient bit = 1 = 3 with 0 remainder ECE 15B Spring 2010

28
Faster Division Can’t use parallel hardware as in multiplier – Subtraction is conditional on sign of remainder Faster dividers (e.g. SRT devision) generate multiple quotient bits per step – Still require multiple steps ECE 15B Spring 2010

29
MIPS Division Use HI/LO registers for result – HI: 32-bit remainder – LO: 32-bit quotient Instructions – div rs, rt / divu rs, rt – No overflow or divide-by-0 checking Software must perform checks if required – Use mfhi, mflo to access result ECE 15B Spring 2010

30
Review Instructions so far: add, addi, sub, addu, addiu, subu mult, div, mfhi, mflo, multu, divu lw, sw, lb, lbu, lh, lhu, sb, shw beq, bne, j, slt, slti, sltu, sltui and, andi, or, ori, xor, xori, sll, srl, sra Registers so far C variables: $s0 - $s7 Temporary variables: $t0 - $t9 Zero: $zero ECE 15B Spring 2010

Similar presentations

© 2021 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google