1. ECE 2372 Modern Digital System Design Section 4.8 Xilinx Schematic Capture Simulation Tutorial

2. Click Start Select Project Navigator

3. Click File

4. Select New Project

5. Name Project Pick a File Location Select Schematic

6. Make These Selections

8. Click Project

9. Select New Source

10. Select Schematic Enter Name

12. Zoom In Click Add Symbol

13. Select Logic Select Part

14. Click and Drop Parts Click Add I/O Markers

15. Click on the End of a Part

16. Right Click to Change Name

17. Select Rename Port

18. Change the Name

19. Click the Wire Tool

20. Click to Add Wires

21. Click the terminal points

22. Complete the Wiring

23. Click Tools / Check Schematic

24. Click Implement Design

25. If you’re lucky, things go well.

26. Select Simulation Click Project

27. Select New Source

28. Name must be different than project name Select Verilog Test Fixture

31. Delete this line

33. Enter Input Signal Values Time Delay Cycle through all combinations Do not forget the “end” statement

34. Click Test Fixture File

35. Click Check Syntax

36. Check Simulate

37. Inputs and Outputs

38. Click Zoom Out several times

39. Verify the design

40. Made a minor change Re-run Simulation