1. Kay Rehlich xTCA Workshop @ RT2012 MicroTCA.4 Timing Distribution and Power Supply Issues

2. MicroTCA.4 Timing Distribution Outline 2 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 MicroTCA.4 connectivity: Precision clocks Bussed clocks and triggers PCIe, Ethernet, SRIO Point-to-point links Power supply issues Noise measurements Grounding Conclusions

3. MicroTCA.4 Timing Distribution 3 Motivation 3 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Backplane Ethernet To Timing Distribution

4. MicroTCA.4 Timing Distribution MTCA.4: Connectivity 4 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 2 radial clocks per AMC: low jitter, configurable direction 2 radial clocks per AMC: low jitter, configurable direction 8 bussed M-LVDS lines: triggers, clocks and interlocks 8 bussed M-LVDS lines: triggers, clocks and interlocks Backplane Ethernet (1) and PCIe (4) Point-2-point: SATA (2) FPGA-2-FPGA (4) Point-2-point: SATA (2) FPGA-2-FPGA (4) Point-2-point: SATA (2) FPGA-2-FPGA (4) Point-2-point: SATA (2) FPGA-2-FPGA (4) Termination

5. MicroTCA.4 Timing Distribution 5 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012

6. MicroTCA.4 Timing Distribution Clock, Gate, Trigger and Interlock Lines Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Radial clocks Point-to-point High precision Both ends terminated Bi-directional Multi-Point LVDS, 8 lines Can be used for: Clocks Triggers Interlocks Data transfer (FPGA-2-FPGA) All AMCs can be Receiver, Transmitter, or disabled … 6

7. MicroTCA.4 Timing Distribution Radial Clocks 7 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Backplane AMC k sender MCH... Crosspoint Switch AMC n receiver AMC m receiver Clock Gen. Clock Gen.... Point-to-point High precision (some ps jitter) Both ends terminated Any AMC can be sender With one MCH: TCLKA and TCLKB usable FCLK for PCIe Low jitter MCH in preparation ADC

8. MicroTCA.4 Timing Distribution 8 M-LVDS Lines: Trigger & Gate Distribution 8 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Backplane AMC k sender... AMC n receiver AMC m receiver Trigger Gen. Trigger Gen.... FPGA L H H One AMC is Master per line Other AMCs can receive All differential lines are terminated on both ends of the backplane

9. MicroTCA.4 Timing Distribution 8 M-LVDS Lines: Interlock Distribution 9 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Backplane AMC k sender... AMC n Sender/receiver AMC m receiver Interlock Gen. Interlock Gen.... FPGA H Interlock Gen. Interlock Gen. H AMC can be Driver only AMC can be Receiver only AMC can be Driver and Receiver

10. MicroTCA.4 Timing Distribution 8 M-LVDS Lines: Data Distribution 10 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Backplane AMC k sender... AMC m receiver FPGA Data Gen. Data Gen. Data Clock Data Clock D0D1D2D3 Data Clock: e.g. 108 MHz Other AMCs can receive For lower speeds one single diff. line is enough

11. MicroTCA.4 Timing Distribution Point-to-Point Communication Links 11 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Backplane AMC k AMC m FPGA Rx Tx Bi-directional ports Several Gbps speed Rx Tx FPGA

12. MicroTCA.4 Timing Distribution Clock and Trigger Transmission 12 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 LVDS M-LVDS Trigger distribution Radial Clock distribution Transition times: 1 ns Rate: <= 500 Mbps Rate: <= 2 Gbps

13. MicroTCA.4 Timing Distribution M-LVDS Specs 13 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Drives: 100 Ohm 2 * 100 Ohm parallel termination Required for Interlocks (wired-or)

14. MicroTCA.4 Timing Distribution XFEL Timing System: 1. Prototype New timing system Fiber optic links 1.3GHz with drift compensation AMC prototype is receiver and transmitter ps stability (< 5ps RMS) Clock, trigger and event distribution 14 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 1.3GHz Clock Data

15. MicroTCA.4 Timing Distribution A Timing System to Sync the Overall Facility Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 15 Receiver Switch Divider 8 line M-LVDS 4* RJ45: 4 * LVDS I/O 9 * LVDS Out FPGA 3 channel transmitter piggyback PCIe Ext. 1.3 GHz ref clock in Optional RTM: 9 transmitters, triggers or clocks TCLKA, TCLKB IN OUT OUT OUT Fiber optics PCB: In Progress Piggyback: ready

16. MicroTCA.4 Timing Distribution Signal Quality and Power Supplies 16 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012

17. MicroTCA.4 Timing Distribution MicroTCA Analog Performance 17 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 ADC With RTM: RMS= 5.86 bits ENOB ~ 11.5 w/o RTM: RMS= 4.9 bits ENOB ~ 11.7 Open transformer: RMS= 67.7 μV 2.22 bits ENOB ~ 12.7 SIS8900 RTM SIS8300 16 bit ADC

18. MicroTCA.4 Timing Distribution Grounding 18 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 220 Volt in = ≈ ADC Linear reg. 12 Volt DC DC/DC chassis ≈ AMC

19. MicroTCA.4 Timing Distribution Understanding Distortions 19 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 © Frank Ludwig, DESY

20. MicroTCA.4 Timing Distribution SIS8300 ADC with 1.3 GHz Down Converter 20 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 Frequency spectrum with bad power supplyFrequency spectrum with good power supply

21. MicroTCA.4 Timing Distribution 600 W Just ready 1200 W in 2012 Managed Power Supplies 21 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012 new Ready this Aug. Noisy 48 V DC in © Wiener

22. MicroTCA.4 Timing Distribution Conclusions MicroTCA.4 offers a variety of connectivity Radial switched clocks Bussed signaling for triggers and data Point-to-point links MicroTCA.4 provides very clean data acquisition One power supply only showed high frequency noise o Excellent performance with fast 16 bit ADCs 22 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012

23. MicroTCA.4 Timing Distribution Thank you! 23 Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012