1. Digital CFEB Prototype Plans 1 B. Bylsma, CSC Upgrade Workshop, Ohio State Univ., April 23-24, 2010 Ben Bylsma The Ohio State University

2. Overview of Design 2 B. Bylsma, CSC Upgrade Workshop, Ohio State Univ., April 23-24, 2010 pre SCA ADC + - ref 16 FPGA 12 bits............ muxmux 21 bits Chan- link 21:3 To DMB over Skewclear 280 Mbps eventLCTRelease Caps ~23.2µS L1A ~3.2µS Analog storage with L1A*LCT coincidence Analog storage - no coincidence Analog storage Digitization and Readout (20µs) Time Line: pre ADC + - ref 16 FPGA 8 pairs............ 6 layers Serial Opt. Trnscvr To DMB over Fiber ~1-2.4Gbps GTX ADC + - 8 8 ref 8 pairs 16 pairs Pipeline/FIFOs Serial LVDS Time Line: eventLCT9.2 to 19.2µSL1A 3.2 to 6.4µS FIFO Readout (6.6 – 12.8µs) Pipeline Digitization Latency xfer L1A·LCT CFEB DCFEB

3. DCFEB Prototype Options: DAQ Path 3 B. Bylsma, CSC Upgrade Workshop, Ohio State Univ., April 23-24, 2010 DAQ Path: Serial LVDS ADC + - ref 16 FPGA 8 pairs............ 6 layers Serial Opt. Trnscvr To Network card ~1Gbps GTX ADC + - 8 8 ref 8 pairs 16 pairs Pipeline/FIFOs pre Chan. Link Skewclear Conn. To DMB over Skewclear 280 Mbps 21 Interface options Interface Options:  Direct Coupling with scaling  AC Coupling with scaling  Single to Differential with Analog Devices ADA4950  Single to Differential with TI THS4524 Output Options:  Compatible with DMB  GbE MAC packets  High Speed Serial Link (Texas Instr. ADS5281) (Analog Devices AD9222) XC6VLX130T-FFG1156 Main Concerns:  Analog Signal Integrity (@interface)  Long pipeline and SEU’s

4. DCFEB Prototype Options: Trigger Path 4 B. Bylsma, CSC Upgrade Workshop, Ohio State Univ., April 23-24, 2010 8 Triad signals pre comp 16............ 6 layers 48 FPGA To TMB over Fiber Serial Opt. Trnscvr ~2.56Gbps GTX Skewclear Conn. 24 lvds pairs Comp. clock To TMB over Skewclear 16 To TMB over fiber Opt. Trnscvr ~1.28Gbps TLK2501 SER/DES Opt. Trnscvr ~1.28Gbps TLK2501 SER/DES Trigger Path: Output Options: A.Current Scheme with 7 cables 48:24 @ 80 MHz B.Reduced Conductors 48:16 @ 120 MHz 48:12 @ 160 MHz C.48 bit Channel Links (not represented) 48:8 @ 280 Mbps D.TLK2501’s and Optical Transcievers 48+16:32:2 @ 2X1.28 Gbps E.GTX in FPGA and Optical Transciever 48+16:1 @ 2.56 Gbps (Multiple rates) Other Notes: Comparator Clock Path Space for output connectors/compatibility FPGA I/Os XC6VLX130T-FFG1156