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10 July 2003Matthew Warren - Trigger Module Update1 CALICE ‘FEDROB’ BE-FPGA Trigger Module Update Matthew Warren University College London 10 July 2003.

Published byCleopatra Scott Modified over 8 years ago

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Presentation on theme: "10 July 2003Matthew Warren - Trigger Module Update1 CALICE ‘FEDROB’ BE-FPGA Trigger Module Update Matthew Warren University College London 10 July 2003."— Presentation transcript:

1 10 July 2003Matthew Warren - Trigger Module Update1 CALICE ‘FEDROB’ BE-FPGA Trigger Module Update Matthew Warren University College London 10 July 2003

2 Matthew Warren - Trigger Module Update2 Trigger Logic Block Diagram (v3 - 25/6/2003) 4x PreTrigger 1x BeamOn 4x Activity 1x Veto 8x Trigger Delayed Trig 1 Delayed Trig 8 ‘Sequencer and Sink’ Seq (8 bit) + Sink (24 bit) RAM = 32KByte RAM ‘Digitiser’ 32bit Shift Registers, Storage Registers (x9) Edge Detect Beam On Sync + Enable 6x Spare 1x Spare SEQ VME Veto Sync + Enable Pre-Trigger Sync + Enables Internal Trig Osc + Random + Timer Activity Sync + Enables 4x SR SEQ VME 4x SR SEQ VME SR VME Trigger Window + Timer VME IRQ SEQ VME Width/ Delay Trigger Sync IRQ SINK VME Trigger Enable, Latch, Shaper, Veto START STOP START STOP J2 EXT NIM 16 In J0 LVDS 5 In VME J0 LVDS 2 Out 1x Trigger 1x Clock 3x Spare J2 BP LVDS 8 Out EXT NIM 16 Out 4x Trigger 1x Clock VME 8 x Counter Delays (16 bit) Clock Control BE FPGA - Trigger Module 4x Spare TTS_J0_READY

3 10 July 2003Matthew Warren - Trigger Module Update3 Trig skew test 0 All signal in Bank 6, fed from a common OR block.

4 10 July 2003Matthew Warren - Trigger Module Update4 Internal Schema... EN Trigs In delay in EN prog delay func SEL Trig Trig En On Trig En Off Trig En VME - Registers

5 10 July 2003Matthew Warren - Trigger Module Update5 More Thinking - Async Latency Tests – requirements/procedures? - Actual functionality - Delays – sub-clock period needs/possibilities? - Integration with main BE-FPGA code? - Interface with Data RAM for easy readout - Register List - Names?

6 10 July 2003Matthew Warren - Trigger Module Update6 Timeline Week Starting (Monday) : 14 July: UCL/HEP Stuff, CALICE Trigger Block Diag 21: Holiday 28: ATLAS (New TIM Arrives from manufacture/RAL) 4 Aug: ATLAS 11: ATLAS / CALICE – Async Trig test 18: CALICE – Main Functional Code 25: CALICE– ditto 1 Sept: CALICE– Integration with BE-FPGA 8: CALICE / ATLAS 15: ATLAS / As required 22: ATLAS / As required 29: As required …

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