1. HO #3: ELEN 384 - Review MOS TransistorsPage 1S. Saha Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure: The gate bias, V G provides the control of surface carrier densities. –For V G < V th ( threshold voltage ), the structure consists of two back to back diodes and only leakage currents flow (  I o of PN junctions), i.e., I D  0 –For V G > V th, inversion layer exists, a conducting channel exists from D  S and current I D will flow. Where V th is determined by the properties of the structure. n+ SD G P

2. HO #3: ELEN 384 - Review MOS TransistorsPage 2S. Saha Long Channel MOS Transistors V th is given by Eq we derived for MOS capacitors. That is, (1)

3. HO #3: ELEN 384 - Review MOS TransistorsPage 3S. Saha 1. NMOSFETs: Band Diagram

4. HO #3: ELEN 384 - Review MOS TransistorsPage 4S. Saha NMOSFETs: Band Diagram

5. HO #3: ELEN 384 - Review MOS TransistorsPage 5S. Saha 2. NMOSFETs: I - V Characteristics

6. HO #3: ELEN 384 - Review MOS TransistorsPage 6S. Saha NMOSFETs: I - V Characteristics

7. HO #3: ELEN 384 - Review MOS TransistorsPage 7S. Saha I  V Characteristics: Basic Equations Note: The depletion region is wider around the drain because of the applied drain voltage V D. The potential along the channel varies from V D @ y = L to 0 @ y = 0 between the drain and source. The channel charge Q I and the bulk charge Q B will in general be f(y) because of the influence of V D, i.e. potential varies along the channel length. +V D +V G P IDID Q I (y) Q B (y) n+ Inversion layer Depletion region

8. HO #3: ELEN 384 - Review MOS TransistorsPage 8S. Saha I  V Characteristics: Basic Equations where W = width of the device V(y) = voltage drop along the channel due to V D Solving the above three Eq we get I D - V D characteristics.

9. HO #3: ELEN 384 - Review MOS TransistorsPage 9S. Saha I  V Characteristics: Basic Equations VDVD IDID VG6VG5VG4VG3VG2VG1VG6VG5VG4VG3VG2VG1 Linear Region Saturation Region V D = V DSAT  I D ((amps) 1/2 ) 

10. HO #3: ELEN 384 - Review MOS TransistorsPage 10S. Saha 3. MOS Device Scaling 3.improve current drive (transconductance, g m ) Benefits of scaling MOSFETs: 1.increase device packing density 2.improve frequency response (transit time)  1/L n+ P L t ox xjxj n+ lolo

11. HO #3: ELEN 384 - Review MOS TransistorsPage 11S. Saha MOS Device Scaling Note that g m and therefore, the current drive of MOSFETs can be increased by: –decreasing the channel length, L –decreasing the gate oxide thickness, t ox Therefore, much of the scaling is driven by decrease in L and t ox.

12. HO #3: ELEN 384 - Review MOS TransistorsPage 12S. Saha MOS Device Scaling Though, MOSFET scaling is driven by scaling down L and t ox, many problems such as increased electric fields are encountered if scaled only these two parameters. In 1974, Dennard et al. proposed a scaling methodology which maintains the electric field in the device constants. (R.H. Dennard, et al., IEEE JSSC, vol. 9, p. 256-268, 1974). Device/circuit parameters Constant field scaling factor Dimension: t ox, L, W, x j, l o 1/K Substrate doping: N a K Supply voltage:V1/K Supply current: I1/K Parasitic capacitance: WL / t ox 1/K Gate delay: CV / I1/K Power dissipation: CV 2 / delay1/K 2

13. HO #3: ELEN 384 - Review MOS TransistorsPage 13S. Saha MOS Device Scaling In practice, constant field scaling has not been strictly observed. Since I D  gate overdrive, (V G – V th ), thus, the demands for high performance have dictated the use of higher supply voltage. However, high supply voltage implies increased power dissipation (CV 2 f). In the recent past, low power applications have become important and have required a scaling scenario with lower supply voltage. Parameters 19701980199020002006 Channel length (  m) 10410.180.10 Gate oxide (nm) 120501541.5 Junction depth (  m) >10.80.30.080.02-0.03 Supply voltage 1253.3-51.5-1.80.6-0.9

14. HO #3: ELEN 384 - Review MOS TransistorsPage 14S. Saha MOS Device Scaling Device/circuit parametersQuasi Constant voltage scaling (K > B > 1) Dimension: t ox, L, W, x j, l o 1/K Substrate doping: N a K Supply voltage:V1/B Ref: B. Davari, et al., Proc. IEEE, April 1995

15. HO #3: ELEN 384 - Review MOS TransistorsPage 15S. Saha 4. Limitations of Scaled MOSFETs A number of factors have been neglected in the simple MOS theory which became increasingly important in scaled devices.  bi,  F, and  ms of S/D junctions were neglected –V th dependence on W, L, and V D is not predicted by simple theory –I  0 for V G < V th. Rather I is exponentially dependent on V G. –Current flow D  S can be initiated by V D rather than V G. This can be modeled by a V th which depends on V D and V G. –Since  fields cannot be held constant because of  bi etc. (and because V D has not been scaled in the industry), higher   higher carrier velocity. Material limits like v sat become important.

16. HO #3: ELEN 384 - Review MOS TransistorsPage 16S. Saha 4(a). Effect of Scaling Down L: V th degradation In long channel MOSFETs, the gate is completely responsible for depleting the semiconductor (Q B ). In very short devices, part of the depletion is accomplished by the drain and source biases. Since less V G is required to deplete Q B, V th  as L . Similarly, as V D , more Q B is depleted by V D and hence V th . This effect dominates in lightly doped substrates.

17. HO #3: ELEN 384 - Review MOS TransistorsPage 17S. Saha Effect of Scaling Down L: Punchthrough If the channel length, L becomes too short, the depletion region from the drain can reach source side reducing e- injection barrier. This phenomenon is known as punchthrough.

18. HO #3: ELEN 384 - Review MOS TransistorsPage 18S. Saha Effect of Scaling Down L: DIBL In very short channel devices: –less V G is required to deplete Q B  the barrier to electron injection from source to drain decreases. –I D  at a given V G. This effect is known as the drain induced barrier lowering (DIBL).

19. HO #3: ELEN 384 - Review MOS TransistorsPage 19S. Saha Effect of Scaling L: Effect of DIBL on I D DIBL results in an increase in I D at a given V G.  V th  as L . Similarly, as V D , more Q B is depleted by V D and hence V th .

20. HO #3: ELEN 384 - Review MOS TransistorsPage 20S. Saha 4(b). Carrier Mobility: Velocity Saturation The mobility of the carriers reduces at higher e-fields in small channel length devices due to velocity saturation (v sat ). As L , while V D  constant: -lateral e-field  -carrier velocity  v sat @ E c  10 4 V/cm for e-.  for nMOSFETs with L < 1  m, v sat causes current to saturate for V D < (V G  V th ).

21. HO #3: ELEN 384 - Review MOS TransistorsPage 21S. Saha Effect of V sat on MOSFET I - V Characteristics MOSFETs with: L = 2.7 um t ox = 500 A (a)(b)(c) (a) Experimental data; (b) simulated data including velocity saturation; (c) simulated data ignoring velocity saturation.

22. HO #3: ELEN 384 - Review MOS TransistorsPage 22S. Saha 4(c). Sub-threshold Conduction For VG < Vth, the surface is in weak inversion and a conducting channel starts to form. As a result, a low level of current flows between the source and drain. In MOS subthreshold slope, S is limited to kT/q (60 mv/dec I)  I D leakage  ; Static power  ; and circuit instability .

23. HO #3: ELEN 384 - Review MOS TransistorsPage 23S. Saha 4(d). Hot Carrier Effects Gate IgIg n+ Drainn+ Source I sub m hole hot e  l llllll V D > V DSAT The maximum e-field at the drain-substrate junction is: As L , in the channel near the drain E max  more rapidly than long L devices. The free carriers passing through the high e-field gain sufficient energy to cause hot-carrier effects.

24. HO #3: ELEN 384 - Review MOS TransistorsPage 24S. Saha Hot Carrier Effects

25. HO #3: ELEN 384 - Review MOS TransistorsPage 25S. Saha I sub flowing into the substrate causes an IR drop in the substrate resulting in Body bias – Substrate Current induced Body Effect (SCBE). –SCBE results in V th drop and manifold increase in  I sub  I DS. Hot Carrier Effects

26. HO #3: ELEN 384 - Review MOS TransistorsPage 26S. Saha 4(e). Band-to-Band Tunneling For small V G ~ 0 and high V D a significant drain leakage can be observed, especially for short channel devices. For V G = 0, and V D high, the e-field can be very high in the drain region causing band-to-band tunneling (BTBT): –BTBT happens only when e-field is sufficiently high to cause a large band bending.

27. HO #3: ELEN 384 - Review MOS TransistorsPage 27S. Saha 4(f). Effect of Scaled Channel Width The depletion region extends sideways in the areas outside the gate controlled region increasing the apparent channel width. As a result V th  opposite to short channel devices.