1. CHAPTER 6: The Little Man Computer
The Architecture of Computer Hardware and Systems Software: An Information Technology Approach
3rd Edition, Irv Englander
John Wiley and Sons 2003
Linda Senne, Bentley College
Wilson Wong, Bentley College

2. The Little Man Computer
Chapter 6 Little Man Computer

3. Mailboxes: Address vs. Content
Addresses are consecutive
Content may be
Data or
Instructions
Address
Content
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4. Content: Instructions
Op code
Operation code
Arbitrary mnemonic
Operand
Object to be manipulated
Data or
Address of data
Address
Content
Op code
Operand
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5. Magic! Load program into memory Put data into In Basket
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6. Assembly Language Specific to a CPU
1 to 1 correspondence between assembly language instruction and binary (machine) language instruction
Mnemonics (short character sequence) represent instructions
Used when programmer needs precise control over hardware, e.g., device drivers
Chapter 6 Little Man Computer

7. Instruction Set Arithmetic 1xx ADD 2xx SUB Data Movement 3xx STORE 5xx
LOAD
Input/Output
901
INPUT
902
Output
Machine Control (coffee break)
000
STOP
COB
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8. Input/Output Move data between calculator and in/out baskets Content
Op Code
Operand
(address)
IN (input) 9 01
OUT (output) 02
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9. LMC Input/Output IN
OUT
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10. Internal Data Movement
Between mailbox and calculator
Content
Op Code
Operand
(address)
STO (store) 3 xx
LDA (load) 5
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11. LMC Internal Data
LDA
STO
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12. Data storage location Physically identical to instruction mailbox
Not located in instruction sequence
Identified by DAT mnemonic
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13. Arithmetic Instructions
Read mailbox
Perform operation in the calculator
Content
Op Code
Operand
(address)
ADD 1 xx
SUB 2
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14. LMC Arithmetic Instructions
ADD
SUB
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15. Simple Program: Add 2 Numbers
Assume data is stored in mailboxes with addresses >90
Write instructions
Input a #
Store the #
Add
Output the
number
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16. Program to Add 2 Numbers: Using Mnemonics
Mailbox
Mnemonic
Instruction Description 00 IN
;input 1st Number 01
STO 99
;store data 02
;input 2nd Number 03
ADD 99
;add 1st # to 2nd # 04
OUT
;output result 05
COB
;stop 99
DAT 00
;data
Chapter 6 Little Man Computer

17. Program to Add 2 Numbers Mailbox Code Instruction Description 00 901
;input 1st Number 01
399
;store data 02
;input 2nd Number 03
199
;add 1st # to 2nd # 04
902
;output result 05
000
;stop 99
;data
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18. Program Control Branching (executing an instruction out of sequence)
Changes the address in the counter
Halt
Content
Op Code
Operand (address)
BR (Jump) 6 xx
BRZ (Branch on 0) 7
BRP (Branch on +) 8
COB (stop)
(ignore)
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19. Instruction Set Arithmetic 1xx ADD 2xx SUB Data Movement 3xx STORE 5xx
LOAD BR
6xx
JUMP
BRZ
7xx
BRANC ON 0
BRP
8xx
BRANCH ON +
Input/Output
901
INPUT
902
OUTPUT
Machine Control (coffee break)
000
HALT
COB
Chapter 6 Little Man Computer

20. Find Positive Difference of 2 Numbers00 IN
901 01
STO 10
310 02 03
STO 11
311 04
SUB 10
210 05
BRP 08
808
;test 06
LDA 10
510
;if negative, reverse order 07
SUB 11
211 08
OUT
902
;print result and 09
COB
000
;stop 10
DAT 00
;used for data 11
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21. Instruction Cycle
Fetch: Little Man finds out what instruction he is to execute
Execute: Little Man performs the work.
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22. Fetch Portion of Fetch and Execute Cycle
1. Little Man reads the address from the location counter
2. He walks over to the mailbox that corresponds to the location counter
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23. Fetch, cont.
3. And reads the number on the slip of paper (he puts the slip back in case he needs to read it again later)
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24. Execute Portion
1. The Little Man goes to the mailbox address specified in the instruction he just fetched.
2. He reads the number in that mailbox (he remembers to replace it in case he needs it later).
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25. Execute, cont.
3. He walks over to the calculator and punches the number in.
4. He walks over to the location counter and clicks it, which gets him ready to fetch the next instruction.
Chapter 6 Little Man Computer

26. von Neumann Architecture (1945)
Stored program concept
Memory is addressed linearly
Memory is addressed without regard to content
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27. Buses There are a number of possible interconnection systems
Single and multiple BUS structures are most common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)
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28. What is a Bus? A communication pathway connecting two or more devices
Usually broadcast
Often grouped
A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels
Power lines may not be shown
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29. Data Bus Carries data Width is a key determinant of performance
Remember that there is no difference between “data” and “instruction” at this level
Width is a key determinant of performance
8, 16, 32, 64 bit
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30. Address bus Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a given location in memory
Bus width determines maximum memory capacity of system
e.g has 16 bit address bus giving 64k address space
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31. Control Bus Control and timing information Memory read/write signal
Interrupt request
Clock signals
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32. Bus Interconnection Scheme
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33. Big and Yellow? What do buses look like?
Parallel lines on circuit boards
Ribbon cables
Strip connectors on mother boards
e.g. PCI
Sets of wires
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34. Physical Realization of Bus Architecture
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35. Single Bus Problems Lots of devices on one bus leads to:
Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance
If aggregate data transfer approaches bus capacity
Most systems use multiple buses to overcome these problems
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36. Traditional (ISA) (with cache)
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37. High Performance Bus
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38. Bus Types Dedicated Multiplexed Separate data & address lines
Shared lines
Address valid or data valid control line
Advantage - fewer lines
Disadvantages
More complex control
Ultimate performance
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39. Bus Arbitration More than one module controlling the bus
e.g. CPU and DMA controller
Only one module may control bus at one time
Arbitration may be centralised or distributed
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40. Centralised or Distributed Arbitration
Single hardware device controlling bus access
Bus Controller
Arbiter
May be part of CPU or separate
Distributed
Each module may claim the bus
Control logic on all modules
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41. Timing Co-ordination of events on bus Synchronous
Events determined by clock signals
Control Bus includes clock line
A single 1-0 is a bus cycle
All devices can read clock line
Usually sync on leading edge
Usually a single cycle for an event
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42. Synchronous Timing Diagram
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43. Asynchronous Timing – Read Diagram
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44. Asynchronous Timing – Write Diagram
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45. PCI Bus Peripheral Component Interconnection
Intel released to public domain
32 or 64 bit
50 lines
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46. PCI Bus Lines (required)
Systems lines
Including clock and reset
Address & Data
32 time mux lines for address/data
Interrupt & validate lines
Interface Control
Arbitration
Not shared
Direct connection to PCI bus arbiter
Error lines
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47. PCI Bus Lines (Optional)
Interrupt lines
Not shared
Cache support
64-bit Bus Extension
Additional 32 lines
Time multiplexed
2 lines to enable devices to agree to use 64-bit transfer
JTAG/Boundary Scan
For testing procedures
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48. PCI Commands Transaction between initiator (master) and target
Master claims bus
Determine type of transaction
e.g. I/O read/write
Address phase
One or more data phases
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49. PCI Read Timing Diagram
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50. PCI Bus Arbiter
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51. PCI Bus Arbitration
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52. Copyright 2003 John Wiley & Sons
All rights reserved. Reproduction or translation of this work beyond that permitted in Section 117 of the 1976 United States Copyright Act without express permission of the copyright owner is unlawful. Request for further information should be addressed to the permissions Department, John Wiley & Songs, Inc. The purchaser may make back-up copies for his/her own use only and not for distribution or resale. The Publisher assumes no responsibility for errors, omissions, or damages caused by the use of these programs or from the use of the information contained herein.”
Chapter 6 Little Man Computer