1. Reading Assignment: Rabaey: Chapter 9
ELEC 516 VLSI System Design and Design Automation Spring 2010 Lecture 11 – Self-time and asynchronous design
Reading Assignment:
Rabaey: Chapter 9
Note: some of the figures in this slide set are adapted from the slide set
of “ Digital Integrated Circuits” by Rabaey, Copyright UCB 2002

2. Characteristic of synchronous design
Function of clock
Ensure physical timing constraints
Clock events serve as a logical ordering mechanism
Advantages
Easy to design, only need to satisfy some simple timing requirement, such as setup time, hold time of the latch/FF
Use clock as global signal
Disadvantages
Clock skew problem
Noise problems due to current flows over a very short period of time, close to the clock edge
Performance is worse, worst case timing instead of average case timing

3. Asynchronous design Eliminate the use of all clocks
Advantage of asynchronous design
Clock skew free
Average case timing
Low power consumption due to elimination of the global clock
Lower voltage noise and electromagnetic emission
Supports ‘plug & play’ property. Each sub-system of asynchronous circuit only needs to care the synchronization with neighborhood sub-systems.
Need to ensure a correct circuit operation that avoids all potential race condition under any operation condition and

4. Self-timed and asynchronous design

5. Self-timed pipelined datapath

6. Handshaking Protocol for self-timed system
Use of Ack(nowledge) and Req(uest) signals
An input word arrives, and a Req signal to the following block (F1) is raised. If F1 is inactive at the time, it transfer the data and acknowledges this fact to the input buffer, which can go ahead and fetch the next word.
F1 is enabled by raising the Start signal. After the computation is completed, the done signal goes high
A Req signal is then issued to F2. If this function is free, an Ack is raised, the output value is transferred, and F1 is freed and can go ahead with its next computation

7. Completion Signal Generation

8. Completion Signal Generation

9. Completion Signal in DCVSL

10. Self-timed Adder

11. Completion Signal Using Current Sensing

12. Hand-Shaking Protocol
Two Phase Handshake

13. Event Logic – The Muller-C Element

14. 2-Phase Handshake Protocol
Advantage : FAST - minimal # of signaling events (important for global interconnect)
Disadvantage : edge - sensitive, has state

15. Example: Self-timed FIFO
All 1s or 0s -> pipeline empty
Alternating 1s and 0s -> pipeline full

16. 2-Phase Protocol

17. Example
From [Horowitz]

18. Example

19. Example

20. Example

21. 4-Phase Handshake Protocol
Also known as RTZ
Slower, but unambiguous

22. 4-Phase Handshake Protocol
Implementation using Muller-C elements

23. Self-Resetting Logic
Post-charge logic

24. Clock-Delayed Domino

25. Asynchronous-Synchronous Interface

26. Synchronizers and Arbiters
Arbiter: Circuit to decide which of 2 events occurred first
Synchronizer: Arbiter with clock f as one of the inputs
Problem: Circuit HAS to make a decision in limited time - which decision is not important
Caveat: It is impossible to ensure correct operation
But, we can decrease the error probability at the expense of delay

27. A Simple Synchronizer • Data sampled on rising edge of the clock
• Latch will eventually resolve the signal value,
but ... this might take infinite time!

28. Synchronizer: Output Trajectories
Single-pole model for a flip-flop

29. Mean Time to Failure

30. Example

31. Cascaded Synchronizers Reduce MTF

32. Arbiters

33. PLL-Based Synchronization

34. PLL Block Diagram

35. Phase Detector
Output before filtering
Transfer characteristic

36. Phase-Frequency Detector

37. PFD Response to Frequency

38. PFD Phase Transfer Characteristic

39. Charge Pump

40. PLL Simulation

41. Clock Generation using DLLs
Delay-Locked Loop (Delay Line Based)
fREF U
Phase Det
Charge Pump DL D
Filter fO
Phase-Locked Loop (VCO-Based)
fREF U PD CP
VCO D ÷N
Filter fO

42. Delay Locked Loop

43. DLL-Based Clock Distribution