Presentation on theme: "Digital Logic Design Lecture # 17 University of Tehran."— Presentation transcript:
Digital Logic Design Lecture # 17 University of Tehran
Outline State Diagram Solving the Counter Problem Using Master Slave Structure Edge Trigger Flip Flops Initialization Some Timing Issues
State Diagram Last session we saw the structure of a SR latch. We can show the things happening in this circuit with a graphical notation called the state diagram. From now on we will observe a state diagram for each structure and then design the circuit from there.
State Diagram (continued…) A direct correspondence can be seen between the transition table of each design and its state diagram. Consider for instance the D latch structure:
Solving the Counter Problem Using Master Slave Structure We saw last session that we are looking for an element to be able to make a memory component of, and as we observed, we weren’t able to use D latches to do this, because of the delay problem and needed clock frequency. To solve this problem we turn our attention to a structure very often seen in building architecture where two complementary working doors are used to control air flow in and out of the building as seen in the figure below:
Solving the Counter Problem Using Master Slave Structure (continued…) Consider using the mentioned idea to control data flow in a D latch using two complementary working latches after each other.
Solving the Counter Problem Using Master Slave Structure (continued…) What's different here is that when the clock pulse goes 1, the output remains stable because the second latch will not let the new data propagate, and when the clock pulse goes 0, the new data (if any) is kept behind the closed door of the first latch until a new clock pulse. This structure is called a D Flip Flop Master Slave.
Solving the Counter Problem Using Master Slave Structure (continued…) In D latches our main problem was the transparency between the output and the input when the clock signal is 1. This problem no longer exists in the master slave D flip flop as there is no longer any direct exposure of the input to the output. We still have the dependence of our circuit on the clock signal, but because the flip flop propagates the input to the output on the falling edge of the clock, the graphical notation is changed as follows:
Solving the Counter Problem Using Master Slave Structure (continued…) We saw how the master slave structure solved our timing problem, but as it had it’s benefits, it still had the problem of a minimum length for its clock pulse, that is if the clock pulse become too short, the input may have not found enough time to reach the second latch at all.
Edge Trigger Flip Flops We have other structures for flip flops as well, for instance the following structure propagates input to the output on the rising edge of its clock pulse:
Edge Trigger Flip Flops (continued…) Quote: All we are looking for here is how the structure operates not how it’s been made. The new structure simply puts the input on the output on the rising edge of the clock pulse:
Edge Trigger Flip Flops (continued…) This way of propagation seems similar to that of the D latch, but here we have kept our output isolation and as the rising edge is only one moment, this structure can’t be considered transparent. The graphical notation of the rising edge flip flop is:
Edge Trigger Flip Flops (continued…) This is the notation use to show rising edge sensitivity to the clock pulse and if a bubble is put in front of it, it shows falling edge sensitivity.
Initialization An issue we have not considered for our structures so far is initialization. For this we need a way to force certain values to the output when and as desired. The red lines shown in the following figure of the rising edge flip flop are use for this aim.
Initialization (continued…) The reason the red lines are linked to both levels of our structure is to support the output from the level before, that is if we were not to have lines on the level to the left, our output could have undergone changes as soon as the resetting signal had been taken off its line, whereas the structure is meant to wait for the next clock signal before undergoing any change. Also note that the reset line has been given priority to the set line by linking it to 3 gates, thus giving its signal a way to deactivate the set line.
Initialization (continued…) The new graphical notation for this structure is: These setting and resetting signals are called asynchronous considering the fact that their effect on the output isn’t controlled by the clock.
Initialization (continued…) Let’s now consider more initializing issues. Consider a problem where we need to initialize many flip flops, either to ‘1’ or ‘0’, through an initialization signal. The structure would look like the following:
Initialization (continued…) What happened in the previous circuit is as follows. When we power up the circuit, the capacitor starts being charged. In this while, before the charge on it goes 1, the flip flops were being initialized through the 0 on the initialization lines. The capacitors can be chosen in a way to give enough time to the flip flops to be initialized.
Initialization (continued…) The timing diagram of the circuit is as follows:
Some Timing Issues There are two problems concerning timing that often occur in digital circuits. The first is clock skew. When a clock signal is used to synchronize different parts of the circuit, if a situation occurs where a clock signal needs to propagate long distances to reach certain flip flop problems can occur. When this happens, a clock distribution logic will help to lessen the clock skew:
Some Timing Issues (continued…) Instead of using a clock distribution, we can make the clock reach all its destinations at a similar time by using a comb distribution such as:
Some Timing Issues (continued…) A second timing issue is the setup and hold time of signals. If a certain value on the D signal is to be used on a certain clock pulse rising (falling) edge, 2 timing factors must not be violated. Firstly the signal D must have its needed value for at least ‘setup time’ before the clock’s rising (falling) edge and must keep this value for at least ‘hold time’ after the clock’s rising (falling) edge.
Some Timing Issues (continued…) This gives the D signal a minimum pulse length of “setup time + hold time” around the particular clock rising (falling) edge.