1. Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering, NTU, Taiwan DAC 2013

2. Outline Introduction Problem Formulation The Enhanced B*-tree Representation Simultaneous Placement and Routing Experimental Results Conclusions

3. Introduction Current-flow and current-density are two major considerations for placement and routing of analog layout synthesis. The current-flow constraint: the nets with monotonic current paths from the VDD to the GND to reduce the parasitic impacts on the current paths. The current-density constraint: the nets with variable wire widths according to the amount of current flowing the nets to avoid IR-drop and electromigration. Schematic M2M1 M4M3 M5 M2M1 M4M3 M5 Current-flowCurrent-density

4. Introduction Current-flow constraintCurrent-density constraint Both current-flow and current-density constraint

5. Problem Formulation The analog layout synthesis problem:  Given a set of modules, a netlist, a set of symmetry groups, a set of current-flow constraints, a set of current-density constraints and the design rules.  Place all modules and route all nets to optimize the chip area, wirelength, bend number, via count such that no design rule is violated and all the current-flow and current-density constraints are satisfied.

6. Review of Hierarchical and ASF-B*-tree m1sm1s m2m2 m6’m6’ m6m6 m2’m2’ m5m5 m 7 s m 8 s m4m4 m3m3 b5b5 b S1 b3b3 b4b4 b S2 b2’b2’ b 1s b6’b6’ b 7s b 8s Symmetry groups: S 1 = {m 1 s, (m 2, m 2 ’)} S 2 = {(m 6, m 6 ’), m 7 s, m 8 s } Hierarchy node Module node Non-symmetry modules: m 3, m 4, m 5 Hierarchical B*-tree ASF-B*-tree

7. The Enhanced B*-tree Representation Simultaneously model modules and interconnects in one topological representation. Two special features are introduced.  Linking-control point  Space node

8. Linking-control point A linking-control point can only connect the wire segments belonging to the same net. A linking-control point contains the information of each connected wire segment, such as the min/max wire width for current-density constraints and the current direction for current-flow constraints.

9. Space node Reserve and allocate routing space for interconnects.  Left space node: the right space beside the module.  Right space node: the top space beside the module. Use physical location candidates to represent the physical location of a linking-control point inside the space node.

10. Symmetry Constraint Handling A symmetry-islandASF B*-treeEnhanced ASF B*-treeModule m 1 ’ with the corresponding space node cluster

11. Simultaneous Placement and Routing

12. Hybrid Perturbations Four new moves for linking-control points:  Delete and insert: delete a linking-control point and insert it to another position  Swap: exchange the positions of two linking-control points  Split: split one linking-control point into two linking-control points  Merge: combine two linking-control points into a new linking- control point

13. Dynamic Routing Resource Reservation and Allocation Allocate the routing resource according to space nodes and linking-control points The routing space R i required by the space node i can be defined as:  L j : the maximum wire width required by linking-control point j.  K j : the number of wire segments connecting to the linking- control point j.

14. Dynamic-Programming-Based Global Routing Integrate with the packing procedure. Record all possible routing topologies with respect to all the physical location candidates of the linking-control point. Satisfy current-flow and current-density constraints.

15. Dynamic-Programming-Based Global Routing The cost C ij to connect the wire segment i with a possible routing topology j:  W ij and B ij are the estimated wirelength and bend numbers to connect the wire segment i with routing topology j.  p is a penalty for unsuccessful routing or constraint violations.

16. Performance-Aware Detailed Routing Simultaneously trace back the sub-problem constructed by DP and detailed route the chosen wire segments. Trace back from a leaf of an enhanced B*-tree. The path which has the lowest cost and satisfies the current-flow and current-density constraints will be chosen and routed. m1m1 m2m2 m3m3 m1m1 m2m2 m3m3 m1m1 m2m2 m3m3

17. The total cost used in SA A: chip area W: routed wirelength B: bend number V: via count p: penalty for unsuccessful routing or constraint violations

18. Experimental Results

21. Conclusions This paper proposed a simultaneous placement and routing algorithm with current-flow and current density constraints for analog circuit designs. Experimental results show that the proposed approach can obtain better layout results and satisfy all specified constraints.