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GATE-LEVEL MODELING (Source: a Verilog HDL Primer by J. Bhasker)

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Presentation on theme: "GATE-LEVEL MODELING (Source: a Verilog HDL Primer by J. Bhasker)"— Presentation transcript:

1 GATE-LEVEL MODELING (Source: a Verilog HDL Primer by J. Bhasker)

2 D IFFERENT L EVELS OF A BSTRACTION Architectural / Algorithmic Level Implement a design algorithm in high-level language constructs. Register Transfer Level Describes the flow of data between registers and how a design process these data. System Algorithm Architecture Register Transfer Level Gate Level Transistor Level

3 D IFFERENT L EVELS OF A BSTRACTION Gate Level Describe the logic gates and the interconnections between them. Switch (Transistor) Level Describe the transistors and the interconnections between them. System Algorithm Architecture Register Transfer Level Gate Level Transistor Level

4 GATE-LEVEL MODELING The gate-level modeling describes the available built-in primitive gates and how these can be used to describe hardware.

5 M ULTIPLE - INPUT G ATES and, nand, or, nor. xor, xnor These logic gates have only one output and one or more inputs.

6 M ULTIPLE - INPUT G ATES Syntax : multiple_input_gate_type[instance_name] (OutputA,Input1,Input2,….,Input1); Note:A value z at an input is handled like an x and the output can never be a z. Multiple-input gate Output A Input1 Input2 Input3

7 M ULTIPLE - INPUT G ATES nand01xz 01111 110xx x1xxx z1xxx and01xz 00000 101xx x0xxx z0xxx or01xz 001xx 11111 xx1xx zx1xx xnor01xz 010xx 101xx xxxxx zxxxx

8 nor01xz 010xx 10000 xx0xx zx0xx xor01xz 001xx 110xx xxxxx zxxxx

9 E XAMPLES : and A1 (Out1, In1, In2) ; and RBX (Sty, Rib, Bro, Qit, Fix) ; xor (Bar, Bud[0], Bud[1], Bud[2] ), (Car, Cut[0], Cut[1] ), (Sar, Sut[2], Sut[1], Sut[0], Sut[3] ) ;

10 M ULTIPLE - OUTPUT G ATES : buf, not These gates have only one input and one or more outputs

11 M ULTIPLE - OUTPUT G ATES : Syntax: multiple_output_gate_type[instance_name] (Out1,Out2,…..,OutN, InputA); InputA Out1 Out2 OutN Out1 Out2 OutN InputA

12 E XAMPLES : BUF B1 ( F AN [0], F AN [1], F AN [2], F AN [3], C LK ) ; NOT N1 (P H A, P H B, R EADY ) ; buf01xz output01xx buf01xz output01xx

13 T RISTATE G ATES : bufif0, bufif1, notif0, notif1 These gates model three state drivers and have one output, one data input and one control input. Note: For a bufif0 gate, the output is z if control is 1, else data is transferred to output. For a bufif1 gate, the output is z if control is 0. For a notif0 gate, the output is z if control is 1, else output is the invert of the input data value. For a notif1 gate, the output is z if control is 0.

14 T RISTATE GATES : Syntax : tristate_gate [instance_name] (OutA, InputB, ControlC); InputAOutputAControlCnotif1 InputAOutputA ControlC notif1 InputAOutputA ControlC notif0 InputAOutputA ControlC bufif1 InputAOutputA ControlC bufif0

15 E XAMPLES : BUFIF BF1 ( D BUS, M EM D ATA, S TROBE ) ; NOTIF 0 NT2 (A DDR, A BUS, P ROBE ) ; Bufif0Control 01xz Data00z0/z 11z1/z xxzxx zxzxx Bufif1Control 01xz Data0z00/z 1z11/z xzxxx zzxxx Notif0Control 01xz Data01z1/z 10z0/z xxzxx zxzxx Notif1Control 01xz Data0z11/z 1z00/z xzxxx zzxxx

16 P ULL G ATES : pullup, pulldown These gates have only one output with no inputs. Note : A pullup gate places a 1 on its output. A pulldown gate places a 0 on its output. Syntax : pull_gate_type[instance_name](OutA); Examples : Pullup PUP(Pwr) ;

17 MOS SWITCHES : cmos, pmos, nmos, rcmos, rpmos, rnmos These gates model unidirectional switches, that is, data flows from input to output and the data flow can be turned off by appropriately setting the control input(s). Note : The pmos( p-type MOS transistor), nmos(n-type MOS transistor), rnmos( r stands for resistive) and rpmos switches have one output, one input, and one control input. If control is 0 for nmos and rnmos switches and 1 for pmos and rpmos switches, the switch is turned off, that is, output has a value z; if control is 1, data at input passes to output.

18 MOS SWITCHES : Syntax: gate_type[instance_name](OutputA, InputB, ControlC); InputBOutput A ControlC nmos switch ControlC OutputAInputB

19 MOS SWITCHES : pmos rpmos Control 01xz Data00z0/z 11z1/z xxzxx zzzxx nmos rnmos Control 01xz Data0z00/z 1z11/z xzxxx zzzxx

20 E XAMPLES : PMOS P1( B IG B US, S MALL B US, G ATE C ONTROL ) ; RNMOS RN1(C ONTROL B IT,R EADY B IT,H OLD ) ; Pcontrol OutputA Ncontrol InputB ( r ) cmos switch

21 B IDIRECTIONAL SWITCHES : tran, rtran, tranif0, rtranif0, tranif1, rtranif1 These switches are bidirectional, that is, data flows both ways and there is no delay when data propagates through the switches. The last four switches can be turned off by setting a control signal appropriately. The tran and rtran switches cannot be turned off. If control is 1 for tranif0 and rtranif0, and 0 for tranif1 and rtranif1, the bidirectional data flow is disabled. Syntax: gate_type[instance_name](SignalA, SignalB, SignalC);

22 G ATE D ELAYS The signal propagation delay from any gate input to the gate output can be specified using a gate delay using the syntax: gate_type [delay] [ instance_name] ( terminal list ); Example: and #3 g (a, b, c);

23 W HEN NO GATE DELAY IS SPECIFIED, THE DEFAULT DELAY IS ZERO. A gate delay can be comprised of up to three values: Rise delay Fall delay Turn-off delay

24 E XAMPLE : 1- BIT M ULTIPLEXER

25 G ATE L EVEL D ESCRIPTION Gate Level: you see only netlist (gates and wires) in the code. a1 a2 in1 in2 sel out o1o1 iv_sel a1_o a2_o n1 iv_sel

26 G ATE -L EVEL M ODELING Steps Develop the Boolean function of output Draw the circuit with logic gates/primitives Connect gates/primitives with net (usually wire) HDL : Hardware Description Language Figure out architecture first, then write code.

27 T EST M ETHODOLOGY Systematically verify the functionality of a model. Procedure of simulation Detect syntax violations in source code Simulate behavior Monitor results

28 T EST M ETHODOLOGY

29 V ERILOG S IMULATOR

30 C ASE S TUDY : F ULL A DDER 30

31 C ASE S TUDY : F ULL A DDER 31 C o = AB + BC i + C i A

32 C ASE S TUDY : F ULL A DDER sum = a  b  c i 32

33 C ASE S TUDY : F ULL A DDER Full Adder Connection Instance ins_c from FA_co Instance ins_s from FA_sum 33

34 T ESTBENCH FOR F ULL A DDER module TestBench; reg a,b,ci; wire sum,cout; initial begin $display(“a b ci sum cout"); a = 1'b0; b = 1'b0;ci = 1'b0; #8 $finish; end always #4 b = ~b; always #2 a = ~a; always #1 ci = ~ci; FA_sum U1(sum,a,b,ci,cout); initial $monitor("%b %b %b %b %b“, a, b, ci, sum, cout); endmodule

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