# 1 Pertemuan 9 Verilog HDL Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01.

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1 Pertemuan 9 Verilog HDL Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01

2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat merumuskan statemen dalam bahasa pemrograman Verilog atas suatu rangkaian gerbang logik sederhana.

3 Basic Concepts A hardware description language (HDL) allows us to specify the components that make up A digital system using words and symbols instead of having to use a pictorial representation like a block or logic diagram.

4 Basic Concepts Behavioral Verification RTL Synthesis Logic design Simulation Circuits Verification Simulation Physical Design Final check Tape Out Architectural features Timing & Dataflow Data storage & movement State machine specification Breakdown into netlist of gates Use netlist to create logic network Cell-based design Custom if needed Layout of mask To manufacturing Example of a VLSI design flow

5 Structural Gate Level Modeling f a b c d G1 G2 G3 W1 W2 Rangkaian digital: module AOI4 (f, a, b, c, d) ; input a, b, c, d ; output f ; wire w1, w2 ; and G1 (W1, a, b) and G2 (f, W1, c, d) nor G3 (f, W1, W2) endmodule Verilog HDL: f = NOT(a. b + c. d) Persamaan logik:

6 Structural Gate Level Modeling in_0 in_1 s_out c_out Rangkaian digital: module Example (s_out, c_out, in_0, in_1) ; input in_0, in_1 ; output s_out, c_out ; xor (s_out, in_0, in_1) ; and (c_out, in_0, in_1) ; endmodule Verilog HDL: Persamaan logik: s_out = in_0  in_1 c_out = in_0. in_1

7 Structural Gate Level Modeling Basics of writing Verilog descriptions Identifier: name of module Value set: 0, 1, x, z Gate Primitives: and, nand, or, nor, xor, xnor, not, buf, bufif0, bufif1, notif0, notif1 Comment Lines: // Comments are useful for documenting code Ports: input, output, inout, reg, wire Gate Delays: 

8 Structural gate Level Modeling 2:1 0 1 mux_out p0 p1 s p0 p1 s s mux_out bufif0 bufif1 MUX menggunakan tri-state primitive: out = p0. s + p1. s module 2_1_mux (out, p0, p1, s) ; input p0, p1, s ; output out ; bufif0 (mux_out, p0, s) ; bufif1 (mux_out, p1, s) ; endmodule Verilog HDL: Persamaan logik:

9 Switch Level Modeling nmos data ctrl out pmos data ctrl out data 0 1 x z 0 1 x z z 0 L L z 1 H H z x x x z z ctrl data 0 1 x z 0 1 x z 0 z L L 1 z H H x z x x z z ctrl Switch-level primitives

10 Design Hierarchies A B F = A. B fet_nand2 A B F = A + B fet_nor2 a b c d out g1 g2 g3 instances fet_and4 Membentuk model gerbang NAND 4 input (NAND4)

11 Design Hierarchies module fet_nand4 (out, a, b, c, d) ; input a, b, c, d ; output out ; supply1 vdd ; wire out_nor, out_nand1, out_nand2 ; fet_nand2 g1 (out_nand1, a, b), g2 (out_nand2, c, d) ; fet_nor2 g3 (out, out_nand1, out_nand2) ; endmodule

12 RTL Modeling RTL (Register Transfer Level) RTL concentrates on specifying the movement of Data among hardware sections. module clock ; reg clk ; //The next statement starts the clock with a value of 0 at t= 0 initial clk = 1’b0 //When there is only statement in the block, no grouping is required always #5 clk = ~clk ; initial #500 \$finish ; // End of the simulation endmodule 0 5 10 15 20 time

13 RESUME Basic Concepts. Structural Gate LevelModeling. Switch Level Modeling. Design Hierarchies. RTL Modeling.

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