1. Characterization Presentation Characterization Presentation OFDM implementation and performance test Performed by: Tomer Ben Oz Ariel Shleifer Guided by: Mony Orbach Duration: Semester

2. motivation Tera-Santa project in the Technion needs implementation. FPGA implementation of OFDM receiver will enable performance test and identification of architecture bottlenecks.

3. Project goals Implementation of an OFDM receiver on a FPGA. Give a good base and tools for future bottlenecks and capability testing.

4. Working environment Simulink via Matlab Xilinx ISE 12.2 Modelsim

5. Top Level Block diagram

6. Demodulator Block diagram Phase multiplier – Shifts the phase of the signal back to its original phase. Inputs: Q in, I in – Current sample’s values; A,B – Correction factors outputs: Q out, I out – The correct signals values. Look Up Table(Qam4) – Translate the signal back to data in bits. Inputs: Q, I – The correct signals values. outputs: QAM4_OUT – The translated data

7. Qam 16 modulation example

8. Phase Multiplier Block diagram IQ multiplier– Shifts the phase of the signal back to its original phase. Inputs: Q in, I in – Current sample’s values; A,B – Correction factors Inputs: Q in, I in – Current sample’s values; A,B – Correction factors outputs: Q out, I out – The correct signals values. TDD– Time Domain Demux Inputs: 8 bits. outputs: D0-3 –each output channels the input data in an upwards order. TDM– Time Domain mux Inputs: D0-3 - 8 bits each. outputs: The output channels the input data in an upwards order.

9. IQ multiplier Block diagram IQ multiplier– Shifts the phase of the signal back to its original phase. First degree (multiplication) Delay is 3 cycles Second degree (adder) Delay is 1 cycle Hence we chose TDD and TDM to have 4 inputs\outputs

10. FFT Testing

11. Sinc function

12. Testing environment DramDram XC5VLX110TXC5VLX110TDramDram Data out Data In countercountercountercounter

13. Gant Diagram 1.4 – 15.416.3 – 31.31.3 – 15.316.2 – 28.21.2 – 15.213.1 – 31.1 Studying Work environment Blocks Design Blocks simulation FPGA integration FPGA simulation