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**A Digital Circuit Toolbox**

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Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

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**Tristate Signals and Busses**

Tristate busses are allowed by most FPGA architectures on devices output pins If tristate are not allowed, the synthesis may have control to automatically substitutes with MUXes

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**Schematics for Internal Tristate Buffer Design**

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**MUX version of Tristate Buffer Design**

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**Bidirectional Busses The signals is divided into two parts:**

the driver part input part The two parts are then wired together

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Bidirectional Busses

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**If/else Priority Encoder**

Implied priority with precedence assigned to the first instruction encountered in a begin/end block

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**If/else Priority Encoder**

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Case Priority Encoder The cases are mutually exclusive and do not overlap

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**State Machines Use a set of registers,**

to determine current machine state Moore style : the output depends only on the state Mealy style: the output depends on the state and some input signals

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State Machines

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State Machines

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**Converting Binary to Gray Code**

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**Converting Gray Code to Binary**

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State Assignment Make a big difference in how efficiently your logic will be synthesize use parameters, ‘define and ‘ifdef to select between encoding assignments

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State Assignment One-hot state assignment means that each state is assigned a single state flip-flop which is active only in the assigned state One-could state assignment means that a flip-flop is inactive only in the assigned state

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Adders Half-Adder The synthesis tool will examine each instance of the operator and will try to implement the logic with a preoptimized module

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Half-Adder

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Full Adder To turn the half adder into a full adder, we take the output of a half adder and connect it into another half adder

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Full Adder

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Full Adder

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Full Adder

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Subtractor Similar to the adder

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Full-Subtractor

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**Hard-Wired Multipliers**

Multiply value by a constant The multiplication process shifts and adds

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Generic Multipliers We must create logic which allows all the shift and adds to be used

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WORKING PRINCIPLE OF DIGITAL LOGIC

WORKING PRINCIPLE OF DIGITAL LOGIC

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