1. Midterm Project Presentation Bandpass Filter on FPGA Student Vitaly Zakharenko Supervisor Mony Orbach Semester Spring 2007 Duration single semester

2. Filter on FPGA requirements Reloadable coefficients High sampling rate Minor finite word length effects (quantization, overflow) Rational use of FPGA resources Low power consumption

3. Two possible implementations Direct VHDL implementation Generation of VHDL via System Generator environment

4. Why System Generator? Simplicity Design in Simulink, no VHDL coding System Gen. Verification Tools Availability of a simple on-the-hardware design verification mechanism from Simulink environment

5. SysGen Building Blocks Simulink blockset of Xilinx - VHDL code generation and simulation Hardware-co simulation block interface - simulation on-the-hardware

6. General SysGen Implementation procedure Step I: Design, simulation and debugging Design and simulation in standard Simulink environment Debugging via Xilinx Wave scope tool

7. General SysGen Implementation procedure Step II: hardware simulation and debugging On-the-hardware simulation in the same Simulink environment using a simulation block interface created by SysGen Debugging via Xilinx Chipscope tool

8. Implementation Testbench view Filter unit (here for software simulation) Hardware Co-simulation unit (on-the-hardware simulation) Filter input generation units

9. Simulation Results Input signal Hardware simulation output signal Software simulation output signal

10. Sample rate reduction signal front end Sample rate reduction coefficient front end Controller Enable inputs controller MAC engines FPGA DRAMs Filter interior view

11. Controller interior view

12. Generic FIR implementation - Any type of filtering possible (low-, high- or bandpass) Multirate implementation providing 8 times the conventional sampling rate filtering Reloadable 256-taps FIR coefficients - Rapid coefficient reload (two signal sample periods) - Exact filtering just after filter reloading (no transient due to reload). One output sample lost when reload is started, the next output sample is the exact output of the new filter. - Many reloads possible before filter restart is required Reduced power consumption for short filters - A special unit takes care MAC engines are enabled only when required Implementation specifications

13. Design Verification and Debugging Step 1) simulation in Simulink and debugging via Wavescope tool of Xilinx Step 2) FPGA bitstream generation and simulation on the hardware (also from the Simulink environment). Debugging in Chipscope.