1. Charge Recycling in MTCMOS Circuits: Concept and Analysis
Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram
Design Automation Conference, rd ACM/IEEE
pp , July, 2006
指導老師: 魏凱城 老師
學 生: 蕭荃泰
日 期: 97年3月24日
彰化師範大學積體電路設計研究所

2. Outline Abstract Charge Recycling Technique
Threshold Voltage and Sizes of Transistors in TG
Wake up Time, Leakage and Ground Bounce Analysis
Simulation Results
Conclusions

3. Abstract
Multi-Threshold CMOS(MTCMOS) technology provides low leakage and high performance operation by utilizing high speed.
In this paper, we propose an appropriate charge recycling technique to reduce energy consumption during the mode transition of MTCMOS circuits.
The proposed method can save up to 46% of the mode transition energy.

4. Charge Recycling Technique
Conventional power gating structure using an NMOS or a PMOS sleep transistor for each circuit block.

5. The proposed charge recycling configuration in power gating structures.

6. Charge recycling technique. TG is replaced by an ideal switch
Charge recycling technique. TG is replaced by an ideal switch. CG and Cp are total capacitance in virtual ground and virtual supply, respectively.

7. Case B: Sleep Transition
Case A: Wake-up Transition
(1)
(4)
(5)
(2)
(6)
(3)
Energy consumption with charge recycling :
Energy saving ratio (ESR) :
(9)
(7) , ,
(10)
Total energy consumption :
(8)

8. charge recycling operation when transitioning from sleep to active mode for an inverter chain in 70nm CMOS technology generated in HSPICE.

9. Threshold Voltage and Sizes of Transistors in TG
Effect of Threshold Voltage

10. Transmission Gate Sizing Effect
Input capacitance of Ctg for transistors of the TG.

11. Wake up Time, Leakage and Ground Bounce Analysis
In charge recycling MTCMOS, the larger the TG size is, the smaller the wake up time of the circuit is.
The increased size, however, increases the dynamic power consumption of the TG.

12. Leakage :
(a) Leakage paths for a conventional MTCMOS structure, (b) Leakage paths for CR MTCMOS structure (c) Δ-Y converted model of (b).
(a)
(b)
(c) － 1
＝1+ 2n

13. We adopt a simple RL model for the purpose of GB analysis.
Ground Bounce (GB):
GB occurs in power gating structures at the sleep to active transition edge.
We adopt a simple RL model for the purpose of GB
analysis.
RL equivalent model of the ground used to analyze GB effect in MTCMOS.

14. GB waveforms in conventional and CR structures for an inverter chain using 70nm CMOS technology.

15. Simulation Results
We used HSPICE to find the wake up time and energy consumption during mode transition for a number of circuits from ISCAS benchmark suite for a 90nm CMOS technology.

16. Conclusions
We showed that by applying the proposed CR technique to the MTCMOS circuits, we can save up to 46% of the mode transition energy while maintaining the wake up time of the original circuit.
We can reduce the negative peak voltage value and the settling time of the ground bounce.

17. The end