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CSE 242A Integrated Circuit Layout Automation Lecture 1: Introduction Winter 2009 Chung-Kuan Cheng.

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Presentation on theme: "CSE 242A Integrated Circuit Layout Automation Lecture 1: Introduction Winter 2009 Chung-Kuan Cheng."— Presentation transcript:

1 CSE 242A Integrated Circuit Layout Automation Lecture 1: Introduction Winter 2009 Chung-Kuan Cheng

2 Agenda Introduction to CSE242A class Topics Class assignments and projects Design challenges ITRS Roadmap

3 Topics of CSE242A ITRS Roadmap and Low Power Design Methodologies Partitioning: (1) Two way partitioning, (2) Multiple way partitioning, (3) Multiple level partitioning, (4) Replication cuts, (5) Performance-driven partitioning, (6) Partitioning for FPGAs. Floorplanning: (1) Floorplanning representations, (2) Block configurations, (3) 3D floorplanning. Placement: (1) Placement algorithms, (2) Local placement, (3) Performance driven placement. Global Routing: (1) Multi-commodity flows, (2) Steiner Trees, (3) Performance driven routing. Detail Routing: (1) Channel routing, (2) Maze routing, (3) PC board routing. Special Net Routing: (1) Bus routing, (2) Clock networks, (3) Net matching, (4) Power/Ground distributions. Cell Layout, Compaction.

4 Class Assignments Homeworks Projects Divided into phases Report and presentation

5 Design Challenges Parallel Processing Power Dissipation New Technologies

6 Theme of Class Combinatorial Algorithms Formulation Engineering Electronic Circuits Physics

7 Scaling Power Interconnect dominance Current density Copper resistivity increases

8 New Technologies 3D Extension Heterogeneous System Low K New Tech Optical Carbon Nano Tube (CNT) Atomic Switch Spintronics

9 Moore’s Law # Trans * 2 / 18 months Product price drop half every 18 month

10 ITRS Roadmap 2007 200720102013201620192022 DRAM ½ pitch (nm) 654532221611 MPU/ASIC m1 ½ pitch 684532221611 High Volumn MPU Chip Size (mm 2 ) 140 Chip local clock (GHz) 4.75.877.349.1811.4714.34 High Performanc e Vdd 1.11.00.90.80.70.65 Low Power Vdd 0.80.70.60.5 0.45

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