1. CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng

2. Outline Menu Multi-Commodity Flow Top-Down Approach Steiner Tree

3. Global Routing Menu

4. Global Routing MCF LP & Duality

5. Net Ordering

6. Global Routing Top-Down Approach

7. 4 2 4 1 T(1)…T(4) T(5)…T(6) T(7)…T(10) T(11) P1 P2 P1P2 P1P2 P3 P1P2 P3 P4

8. Linear Programming H1 V1 H2 V2

9. Steiner tree

10. Maze Routing Breadth First Search: Map memory reduction 1 2 1 1 2 2 2 1 1 2 2 1 1 2 2 1 1 1 2 2 1 1 S 1 1 1 2 2 1 1 1 1 2 2 1 2 2 1 2 2 2 1 2 1 1 3 1 1 3 2 3 1 1 3 2 1 2 1 3 2 1 S 1 1 3 2 1 2 1 3 2 3 1 1 3 1 1 A sequence that guarantees the predecessor is different from its successor. # states: 1, 2, Empty, Filled, 1, 2, 3

11. Speed-up Limit to a bounding box * 120% Start from two ends Expand from the corners farthest from the center Expand the frontier closer to the target first s t

12. Depth First Search 1 2 2 33 4 4 5 Line probe

13. A * router s i t

14. Ripup and Reroute Net sequence ordering Penalty function on overlapping Route around existing wires Plowing or compaction Topological routing A B C

15. Ripup and reroute with cost driven router

16. Overlap Model

17. 8 32 547 6 1 12 345 678

18. Hybrid Router

20. River Routing Net Ordering For each pin (circular order) If it is a starting pin, push Else if is ending pin, pop into a queue. Route nets to follow contour 3 2 4 423 55 66

21. Planar Routing Power & Ground Distribution Find a cut line that separates the chip into two regions Obj: min tree length P + treelength G P G G P P G

22. Gate Matrix A B A B Vdd 1 2 3 4 5 A 6 B 7 8A B 9 10 Z

23. AB C Z 1 3 6 9 2 4 7 5 8

24. Cell Generation Vdd AB C D A B CD Z A B C D Z A B C D Z

25. Z D D1 1 22CC Z A 4 A 4 B 3 B 3

26. Find an Euler path on graph G & its dual with same sequence of labels Given serial & parallel graph, the operation is commutative 1 2 3 2 3 1 22 11

27. Compaction S t 112345 6 78 9 ‘

28. Compaction with Wire Jogging

29. Compression ridge 45 degree path