1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 21 - Floorplanning Spring, 2007

2. ECE 425 Spring 2007Lecture 21 - Floorplanning2 Announcements  Reading  Book: 7.1 - 7.4  Where We Are  Last Time: Packaging I/O Pads MOSIS Pad Cells and the Project Pad Frame  Today Floorplanning

3. ECE 425 Spring 2007Lecture 21 - Floorplanning3 Floorplanning Overview  Floorplanning determines  Shape & placement of major blocks  Power/Ground Network Design  Clock Network Design  General Wiring Design data path RAM std cell

4. ECE 425 Spring 2007Lecture 21 - Floorplanning4 Purposes of Floorplanning  Early in design:  Determine placement, shape, & orientation of blocks  Budget: Area: block, wiring Delay  Negotiate tradeoffs between blocks (exploit flexibility in modules)  Late in design:  Use as guideline for chip assembly  Make sure the pieces fit together as planned  Make sure wiring is completed successfully

5. ECE 425 Spring 2007Lecture 21 - Floorplanning5 Floorplanning Concerns  Assign locations to blocks of different shapes and sizes  Wiring Concerns  Location of routing regions  Power/Ground Wiring  Clock Wiring  General connection wiring  Special case of the placement problem

6. ECE 425 Spring 2007Lecture 21 - Floorplanning6 Block Placement  Blocks have:  Area - usually fixed  Aspect ratio - often changeable  Orientation - may be rotated, reflected  Location - physical location on chip  Goal: find a placement of all blocks that “fits”

7. ECE 425 Spring 2007Lecture 21 - Floorplanning7 Blocks and Wiring  Cannot ignore wiring during block placement  Large wiring areas may force rearrangement of blocks.  Wiring plan must consider area and delay of critical signals.  Blocks divide wiring area into routing channels.

8. ECE 425 Spring 2007Lecture 21 - Floorplanning8 Demonstration - Simplified Floorplanning Applet  Blocks may be rotated, reflected  Wirelength estimated by “rat’s nest”  One possible algorithm: simulated annealing

9. ECE 425 Spring 2007Lecture 21 - Floorplanning9 Floorplanning and Routing  Floorplanning determines routing regions  Connections between pins can cross several routing regions

10. ECE 425 Spring 2007Lecture 21 - Floorplanning10 Types of Routing Regions  Channels - connections on 2 sides, variable height  Switchboxes - connections on 4 sides, fixed height channelswitchbox channel switchbox pins

11. ECE 425 Spring 2007Lecture 21 - Floorplanning11 Detailed Routing Types of Routing  Global routing (“Loose routing”)  Assign wires to routing regions  But don’t assign exact wiring locations  Often done at same time as floorplanning  Detailed routing  Assign wires to exact location - tracks  Applied to one routing region at a time  Usually done in final chip assembly Global Routing

12. ECE 425 Spring 2007Lecture 21 - Floorplanning12 Floorplanning Steps Block Placement Routing Region Definition Global Routing Detailed Routing Early Floorplanning Chip Assembly

13. ECE 425 Spring 2007Lecture 21 - Floorplanning13 Routing Region Definition  Routing regions defined by block boundaries  Different configurations are possible A BC channel 1 ch 2 ch 1ch 2 ch 3

14. ECE 425 Spring 2007Lecture 21 - Floorplanning14 A B C C Placement effects Routing Regions  Changing spacing changes relationship between block edges:

15. ECE 425 Spring 2007Lecture 21 - Floorplanning15 Routing Region Abstraction: Channel Graph  Nodes represent routing regions  Undirected edges represent adjacency  Used for global routing w/ modified Lee Algorithm A B C D E

16. ECE 425 Spring 2007Lecture 21 - Floorplanning16 Line probe routing  Heuristic method for finding a short route.  Works with arbitrary combination of obstacles.  Does not explore all possible paths—not optimal.

17. ECE 425 Spring 2007Lecture 21 - Floorplanning17 line 2 Line Probe Example A A B B

18. ECE 425 Spring 2007Lecture 21 - Floorplanning18 Detailed Routing  Channel routing:  channel may grow in one dimension to accommodate wires  pins generally on only two sides.  Traditional approach: Left-Edge Algorithm  Switchbox routing:  cannot grow in any dimension;  pins are on all four sides, fixing dimensions of the box.  Traditional approach: Maze Routing or variant

19. ECE 425 Spring 2007Lecture 21 - Floorplanning19 channel B Detailed Routing and Channel Ordering  Detailed routing of one region determines pins for adjacent regions  This creates an ordering constraint channel A End pin

20. ECE 425 Spring 2007Lecture 21 - Floorplanning20 A B C D Ordering Conflicts - Windmills  Circular ordering constraint  No feasible routing

21. ECE 425 Spring 2007Lecture 21 - Floorplanning21 Slicable floorplan  Created by recursive slicing  Never contains windmills - routability guaraneteed

22. ECE 425 Spring 2007Lecture 21 - Floorplanning22 Power distribution  Must size wires to be able to handle current— requires designing topology of V DD /Gnd networks.  Want to keep power network in metal—requires designing planar wiring.

23. ECE 425 Spring 2007Lecture 21 - Floorplanning23 ` Low-resistance jumper  We want to avoid this:

24. ECE 425 Spring 2007Lecture 21 - Floorplanning24 Interdigitated power and ground lines V DD Gnd

25. ECE 425 Spring 2007Lecture 21 - Floorplanning25 Power tree design  Interdigitated power, ground trees  Recall rules for metal migration - current density < 1.5mA/µm  Each branch must be able to supply required current to all of its subsidiary branches  Size buses by recursively estimating peak currents

26. ECE 425 Spring 2007Lecture 21 - Floorplanning26 cell V DD V SS Planar power/ground routing theorem  Draw a dividing line through each cell such that all V DD terminals are on one side and all Gnd terminals on the other.  If floorplan places all cells with V DD on same side, there exists a routing for both V DD and Gnd which does not require them to cross.

27. ECE 425 Spring 2007Lecture 21 - Floorplanning27 A B C V DD V SS V DD V SS cut line no cut line no connection Planar routing theorem example

28. ECE 425 Spring 2007Lecture 21 - Floorplanning28 Power supply noise  Variations in power supply voltage manifest themselves as noise into the logic gates.  Power supply wiring resistance creates voltage variations with current surges.  Voltage drops on power lines depend on dynamic behavior of circuit.

29. ECE 425 Spring 2007Lecture 21 - Floorplanning29 Tackling power supply noise  Must measure current required by each block at varying times.  May need to redesign power/ground network to reduce resistance at high current loads.  Worst case, may have to move some activity to another clock cycle to reduce peak current.

30. ECE 425 Spring 2007Lecture 21 - Floorplanning30 Clock distribution  Goals:  deliver clock to all memory elements with acceptable skew;  deliver clock edges with acceptable sharpness.  Clocking network design is one of the greatest challenges in the design of a large chip.

31. ECE 425 Spring 2007Lecture 21 - Floorplanning31 Clock delay varies with position

32. ECE 425 Spring 2007Lecture 21 - Floorplanning32  H-tree

33. ECE 425 Spring 2007Lecture 21 - Floorplanning33 Clock distribution tree  Clocks are generally distributed via wiring trees.  Want to use low-resistance interconnect to minimize delay.  Use multiple drivers to distribute driver requirements—use optimal sizing principles to design buffers.  Clock lines can create significant crosstalk.

34. ECE 425 Spring 2007Lecture 21 - Floorplanning34 Clock distribution tree example

35. ECE 425 Spring 2007Lecture 21 - Floorplanning35 Floorplanning tips  Develop a wiring plan. Think about how layers will be used to distribute important wires.  Sweep small components into larger blocks. A floorplan with a single NAND gate in the middle will be hard to work with.  Design wiring that looks simple. If it looks complicated, it is complicated.

36. ECE 425 Spring 2007Lecture 21 - Floorplanning36 Floorplanning tips, cont’d.  Design planar wiring. Planarity is the essence of simplicity. It isn’t always possible, but do it where feasible (and where it doesn’t introduce unacceptable delay).  Draw separate wiring plans for power and clocking. These are important design tasks which should be tackled early.

37. ECE 425 Spring 2007Lecture 21 - Floorplanning37 Floorplanning the A/D Project  Placement of key components  Place to make wiring easy to pads  Place to make wiring easy between components  Alter orientation of cells if helpful (sideways / upsidedown)  Power/Ground Routing  Follow interdigitated tree if possible  Analog concern: separate power for DAC (VRPlus/VRMinus)  General Signal Routing  Try to make connections simple  Use pin placement to aid in routing SAR  Magic “routing mode” very helpful

38. ECE 425 Spring 2007Lecture 21 - Floorplanning38 Floorplanning the Project Location: /usr14/cad/PadFrame/adcframe04.mag 2570 1060 2570 DAC Comp. SAR

39. ECE 425 Spring 2007Lecture 21 - Floorplanning39 Validating Chip-Level Designs  Simulate, simulate, simulate!  IRSIM for digital stuff  PSpice for analog stuff AND entire chip core Check for proper function Measure power supply current to verify power/gnd network sizing  Inspect layout for fatal errors  Power/Ground connections (magic “s” macro helpful!)  Watch for accidental Vdd/Gnd shorts!  Missing substrate contacts  Missing n-wells (with missing substrate contacts)  Be paranoid - re-check after changing!

40. ECE 425 Spring 2007Lecture 21 - Floorplanning40 Coming Up  Chip-Level Design: Case Studies  Subsystem Design