1. 1 CSE-308 Digital System Design (DSD) N-W.F.P. University of Engineering & Technology, Peshawar

2. Loop Statements Repeat While For

3. Modeling Synchronous Logic with Cyclic Behaviors Use edge-sensitive cyclic behaviors to model flip-flops and sequential logic. always @ (posedge clock, negedge reset) begin // procedural statements go here end Edge qualifier Execute cyclically Event control operator Execute when the clock has a rising edge or the reset has a falling edge. Sensitivity List

4. Modeling Synchronous Logic (1 of 2) Example: D Flip-Flop with asynchronous set / reset module df_behav (input data, set, clk, reset, output reg q, output q_bar ); assign q_bar = ~ q; always @ (posedge clk, negedge reset, negedge set) begin if (reset == 0) q <= 0; else if (set == 0) q <= 1; else q <= data; end endmodule Non-blocking assignment operator How does a synthesis tool identify the synchronizing signal? df_behav clk dataq reset set q_bar

5. Modeling Synchronous Logic (2 of 2) Example: D flip-flop with synchronous set / reset module df_behav (input data, set, clk, reset, output reg q, output q_bar ); assign q_bar = ~ q; always @ (posedge clk) // Flip-flop with synchronous set/reset begin if (reset == 0) q <= 0; else if (set == 0) q <= 1; else q <= data; end endmodule

6. Generating Clock and Reset!! Initial // All the initializations should be in the initial block begin clk = 0; # 5 rst_n = 0; // pull it low # 2 rst_n=1; // pull it high end always @(clk) // generated clock #10 clk=(~clk); -------------------------------------------------------------------------------- // resetting inside the module always @ (posedge clk or negedge rst_n) begin If (! rst_n) // If rst_n=0 reg a <= 4’b0; else a_reg <= a; end

7. Example: Accumulator a acc_out sum

8. module acc(a, clk, rst_n, acc_out); input [3:0] a; input clk, rst_n; output [7:0] acc_out; reg [7:0] acc_out; reg [7:0] sum; always @(a or acc_out) sum = a + acc_out; always @(posedge clk or negedge rst_n) begin if(!rst_n) acc_out <= 0; else acc_out <= sum; end endmodule module test; reg [3:0] A; reg CLK, RST_N; wire [7:0] ACC_OUT; integer i; acc ACC0(A, CLK, RST_N, ACC_OUT); initial begin #5 RST_N = 0; #2 RST_N = 1; end initial begin #5 A = 1; for(i=0; i<10; i=i+1) #20 A = A + 1; end always #10 CLK = ~CLK; initial $monitor($time, " A=%d, sum=%d, ACC_OUT=%d", A, ACC0.sum, ACC_OUT); initial #60 $stop; endmodule

9. ANSI-Style port lists Module mux8 ( output reg [7:0] y, input wire [7:0] a, Input wire en );

10. A Combinational Circuit Using behavioral constructs –Logic for a simple MUX is specified procedurally here –This example is synthesizable module MUX(f, sel, b, c); output regf; input sel, b, c; always @ (sel or b or c) begin if (sel == 1) f = b; else f = c; end endmodule Read this as follows: Wait for any change on sel, b, or c, then execute the begin-end block containing the if. Then wait for another change. Read this as follows: Wait for any change on sel, b, or c, then execute the begin-end block containing the if. Then wait for another change. This “if” functionally describes the MUX f b c

11. Huh? Is It Really Correct? WWWWaaaaaiiiiiitttt a minute? –Where’s the register? The synthesis tool figures out that this is a combinational circuit. Therefore, it doesn’t need a register. The register is there as an “artifact” of the description — things on the left-hand side have to be registers. –How does it figure out that this is combinational? The output is only a function of the inputs (and not of previous values) Anytime an input changes, the output is re-evaluated f b c module MUX (f, sel, b, c); output reg f; input sel, b, c; always @ (sel or b or c) begin if (sel == 1) f = b; else f = c; end endmodule ?

12. The Basic Rules The rules for specifying combinational logic using procedural statements –Every element of the input set must be in the sensitivity list –The combinational output must be assigned in every control path So, we’re saying that if any input changes, then the output is re- evaluated. — That’s the definition of combinational logic. module MUX (output reg f, input sel, b, c); always @ (sel or b or c) begin if (sel == 1) f = b; else f = c; end endmodule

13. What If You Mess Up? If you don’t follow the rules...? –Verilog assumes you are trying to do something clever with the timing –It’s legal, but it won’t be combinational module blah (output reg f, g; input a, b, c); always @ (a or b or c) begin if (a == 1) f = b; else g = c; end endmodule What’s wrong? This says: as long as a==1, then f follows b. (i.e., when b changes, so does f.) But, when a==0, f remembers the old value of b. Combinational circuits don’t remember anything! This says: as long as a==1, then f follows b. (i.e., when b changes, so does f.) But, when a==0, f remembers the old value of b. Combinational circuits don’t remember anything! f doesn’t appear in every control path in the always block (neither does g).