1. Advanced Digital Design The Need for a Design Style by A. Steininger Vienna University of Technology

2. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 2 Outline Skew versus consistency Skew versus consistency The need for a design style The need for a design style Hazards, Glitches & Runts Hazards, Glitches & Runts

3. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 3 Design: Boolean Logic unambiguous functional description unambiguous functional description combinational logic: truth table sequential logic: state diagram technology agnostic technology agnostic temporal relations are not relevant temporal relations are not relevant (just sequence)

4. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 4 Implementation: Physics There is a signal delay There is a signal delay in all transistors through all interconnect This signal delay This signal delay cannot be eliminated is indeterministic Why ?

5. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 5 Fundam. Speed Limitations EM wave propagation EM wave propagation (20cm/ns) Information can never travel faster than with speed of light. (20cm/ns) Charging effects Charging effects (t   = RC) Charging of a capacitance with limited current takes time. (t   = RC) Charge movement Charge movement (0,1mm/s) Movement/diffusion of charges in semi- conductor has limited speed. (0,1mm/s) Fundamental law of physics inevitable material-immanent

6. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 6 Can we predict Delay? Gate Delay Gate Delay logic depth (<=optimization & mapping) data dependent delay (dynamic!) Interconnect Delay Interconnect Delay geometry (lengths, capacitances) vias, switches crosstalk (dynamic!) PVT Variations PVT Variations P Process variations V supply Voltage T Temperature

7. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 7 Skew Prediction ? Signal delay is difficult to predict, it even varies with operating conditions & data. Signal delay is difficult to predict, it even varies with operating conditions & data. The delays along two individual signal paths will never be the exactly the same. The delays along two individual signal paths will never be the exactly the same. The (maximum) difference among two or more signal paths of interest – termed „skew“ – is even more difficult to predict. The (maximum) difference among two or more signal paths of interest – termed „skew“ – is even more difficult to predict. ? ?

8. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 8 Skew and Consistency Data consistency Data consistency When individual data items are interpreted together, these must belong to the same context they must be temporally correlated they must be temporally correlated x- and y-coordinates of a moving object bits of a data word Skew distorts temporal correlation

9. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 9 receiving 00 10 11 10 00 Consistency – an Example sending 00 10 11 10 00 receiving 00 10 11 10 00 receiving 10 10 01 00 00 Delay Skew

10. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 10 Y = A   A  0 1 0 A 1 0 1 0 0 TT Everything OK for the steady state A dynamic analysis reveals glitches! Consistency & Glitches

11. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 11 Pulse & Glitch Pulse: Pulse: transition followed by opposite one „positive“:  „negative:  Pulse width PW: Pulse width PW: time distance between these transitions Glitch: Glitch: spurious pulse, usually undesired PW

12. Danger of a Glitch Glitch becomes dangerous when converted from spurious to steady state Glitch becomes dangerous when converted from spurious to steady state by using the transition (control signal) or by capturing its value (data signal) Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 12

13. Types of Delay Pure delay (transport delay) Pure delay (transport delay) simple „time shift“ of all transitions pulses of any width are transported Inertial delay (component delay) Inertial delay (component delay) transition only made if still required after delay pulses shorter than the delay are suppressed Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 13     pure pure = inertial inertial

14. Delay types in Reality Pure delay Pure delay much related to speed-of-light delay typical for wires with small RC increasing relevance for newer technology Inertial Delay Inertial Delay much related to RC delay typical for gates (& wires with high RC) considered more relevant in practice Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 14

15. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 15 Runt Pulses when decreasing width PW of pulse applied to real circuit, when decreasing width PW of pulse applied to real circuit, large PW => pulse definitely recognized small PW => pulse definitely ignored (circuit‘s inertial delay) some PW in between  RUNT pulse for some PW in between output will be very short and not reach full amplitude  RUNT pulse marginally recognized a runt will be marginally recognized (may or may not) by subsequent inputs VDD VSS

16. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 16 Design: Boolean Logic unambiguous functional description unambiguous functional description combinational logic: truth table sequential logic: state diagram technology agnostic technology agnostic temporal relations are not relevant temporal relations are not relevant (just sequence) cannot be expressed!

17. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 17 The Consequences without consideration of time Boolean Logic describes I/O-mapping without consideration of time continuously consistent This implies continuously consistent inputs invalid dynamic outputs  glitches & runts Skew inevitably causes inconsistency at the inputs and hence invalid dynamic outputs  glitches & runts ABCF 0000 0010 0101 0111 1000 1011 1100 1111 A

18. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 18 single bit at a time Just change a single bit at a time, then skew does not take effect Data permanently consistent (  „Huffman Circuits“) A Skew REALLY? Why not avoid Skew?

19. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 19 Still glitches… 1 1 1 0   Glitch! single transition Forks Forks turn single transitions into multiple ones !

20. Some First Conclusions… Boolean Logic is a powerful method for functional description, but Boolean Logic is a powerful method for functional description, but it does not take care of timing issues it does not take care of timing issues Timing issues are relevant, their ignorance leads to glitches, runts and inconsistent data Timing issues are relevant, their ignorance leads to glitches, runts and inconsistent data  We need a some form of „discipline“ when designing a real circuit  It makes sense to investigate further into glitches Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 20

21. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 21 Combinational Hazard Potential for glitches to occur in a circuit, depending on relative path delays Potential for glitches to occur in a circuit, depending on relative path delays Glitch is a manifestation of a hazard in a physical implementation of the circuit Glitch is a manifestation of a hazard in a physical implementation of the circuit Actual manifestation may depend on Actual manifestation may depend on input patterns actual delay values (  PVT variations)

22. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 22 Types of Comb. Hazards static 1: static 1: input change retains output at 1, but negative glitch occurs static 0: static 0: same for output 0 and positive glitch dynamic: dynamic: glitch occurs prior to desired output change

23. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 23 Static 0 Hazard Fundamental circuit structure: Fundamental circuit structure: fork inversion on one lane reconvergent into AND gate Y = A  A  0 A

24. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 24 Static 1 Hazard Fundamental circuit structure: Fundamental circuit structure: fork inversion on one lane reconvergent into OR gate Y = A  A  1 A

25. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 25 Eliminating SC Hazards How to choose delay constraints ? How to choose delay constraints ? no solution for constant delays no solution for constant delays solvable for edge-dependent delay:  :  1 >  2  :  1  2  :  1 <  2 A Y  

26. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 26 Delay constraints Absolute timing contraints: Absolute timing contraints: keep skew between different paths within a certain limit  generally not achievable Relative timing constraints: Relative timing constraints: keep one path slower than the other  generally possible,  generally possible, particularly in combination with input restrictions

27. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 27 Detection in Schematics A Y B C D

28. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 28 Detection in Equation assign input values until B and B remains: assign input values until B and  B remains: A = 0; C = 0; D = 1 (enabling condition, need not exist) Y = B  B static 0 hazard Y = [(C  D)(B  D)]  (A  B  C)

29. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 29 Detection in KV-Diagram 1111 11 1 A B C D static 1 hazards 1110  1111 0110  0111 remedy: redundant term static 0 hazards use KV for Y

30. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 30 F = (X  Y  Z)  (W  Z)  (W  Y) 1 1 1 1 1 1 1 1 1 1 00 01 11 10 00 01 11 10 W Z Y X YZ WX 1 W 1 1 11 1 1 1 00 01 11 10 00 01 11 10 Z Y X YZ WX F = (X  Y  Z)  (W  Z)  (W  Y) 1 1 Another Example  (Y  Z)  (W  X  Y)  (W  X  Z) A

31. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 31 Systematic Approach define a notation to describe all scenarios of interest define a notation to describe all scenarios of interest 9-valued logic study propagation study propagation extended truth table identify critical input scenarios identify critical input scenarios satisfyability problem

32. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 32 9-valued logic 1stable high 0stable low rising edge falling edge S1static-1-hazard S0static-0-hazard D+dynamic hazard, rising edge D-dynamic hazard, falling edge *any value at all ordering: S0 > 0, S1 > 1, D- >, D+ > This is NOT the IEEE 1164 logic!

33. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 33 Truth Table „AND“ &01S1S0D+D-* 0 1   S1 S0 D+ D- *

34. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 34 Truth Table „AND“ &01S1S0D+D-* 0000000000 101S1S0D+D-* 0S0D-S0S0D-* 0S0D+S0D+S0* S10S1D-D+S1S0D+D-* S00S0S0S0S0S0S0S0* D+0D+S0D+D+S0D+S0* D-0D-D-S0D-S0S0D-* *0********

35. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 35 Propagation Analysis 1 A Y    S0

36. Single Input Change (SIC) So far: glitch due to single input signal changing So far: glitch due to single input signal changing Watch out for reconvergent paths: Watch out for reconvergent paths: Fork: put single transition on concurring paths Join: recombine the two transitions, whose temporal relation has been distracted by skew If we allow more input signals to change If we allow more input signals to change we do not need the fork by moving the relative position of the inputs we gain even more freedom in arranging adverse timing conditions Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 36

37. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 37 Multiple-input change A Y B C D

38. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 38 MIC Detection in Equ. assign input values for A and B: assign input values for A and B: A = 1; B = 0 Y = C  D static 0 hazard: 1000  1011 Y = [(C  D)(B  D)]  (A  B  C)

39. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 39 MIC Detect in KV-Diag. 1111 11 1 A B C D There is a shortest path leading over other logic value „functional hazard“ cannot be eliminated

40. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 40 Handling Static Hazards Elimination Elimination add terms (in sum-of-products implem.) not always possible for MIC Defeating Defeating disallow enabling conditions disallow critical transition(s) restriction of operation add timing constraints needs to be asymmetric Filtering Filtering (i.e. adding inertial delay) limited effect only, slows down circuit

41. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 41 Dynamic Comb. Hazard Fundamental circuit structure: Fundamental circuit structure: A edge producer glitch producer (010)

42. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 42 Dynamic Comb. Hazard Fundamental circuit structure (dual): Fundamental circuit structure (dual): A edge producer glitch producer (101)

43. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 43 Dynamic combin hazards  safe if  1 <  2 or  3 <  1 (no glitch)(edge masks glitch)  safe if  1 >  2 or  3 >  1 all safe if  1 >  2,  3 or  1  2,  3 or  1 <  2,  3 A 1111 2222 3333

44. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 44 Extension to MIC A A B C

45. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 45 Dynamic Hazards ? A Y B C D

46. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 46 Handling Dynamic Hazards Elimination Elimination not always possible for MIC Defeating Defeating relative constraints sufficient! in complex circuits unclear if constraining always possible: constraints may be contradicting BUT not all input patterns occur disallow enabling patterns disallow critical transitions Filtering Filtering

47. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 47 What about „real“ HW? Switching involves 2 transistors per input  even more delay path combinations (p-stack, n-stack)  may lead to tristate, short, glitch,…  proper cell layout is crucial! Example AOI gate:

48. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 48 So why a Design Stlye? Skew is inevitable and unpredictable Skew is inevitable and unpredictable It causes inconsistent transient states It causes inconsistent transient states Their logic evaluation causes runts & glitches Their logic evaluation causes runts & glitches These are harmful if converted to stable states These are harmful if converted to stable states There are methods to detect and prevent glitches; those are far from perfect There are methods to detect and prevent glitches; those are far from perfect Specific precautions are needed, as Boolean Logic does not help here  we need some discipline, a design style Specific precautions are needed, as Boolean Logic does not help here  we need some discipline, a design style

49. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 49 Without a Design Style… …combinational gates may, due to race conditions, receive contradictory signals „simultaneously“ on different inputs, hence …combinational gates may, due to race conditions, receive contradictory signals „simultaneously“ on different inputs, hence create glitch or runt pulses that may create glitch or runt pulses that may be converted into erroneous stable states or be converted into erroneous stable states or even cause metastability in storage loops. even cause metastability in storage loops. These glitches, runts and/or manifestations of metastability may propagate, and These glitches, runts and/or manifestations of metastability may propagate, and they may be subject to „Byzantine“ inter- pretation, causing further erroneous states. they may be subject to „Byzantine“ inter- pretation, causing further erroneous states.