1. Ch. 12 Cache Direct Mapped Cache

2. Comp Sci 251 -- mem hierarchy 2 Memory Hierarchy Registers: very few, very fast cache memory: small, fast main memory: large, slow secondary memory (disk): huge, very slow Example: http://www.dell.com/content/products/category.aspx/vostrodt?c=us&cs=04&l=en&s=bsd

3. Comp Sci 251 -- mem hierarchy 3 Memory Hierarchy Registers: very small, very fast cache memory: small, fast  Up to Intel® CoreTM 2 Duo E6700 (2.60GHz, 4MB L2 cache, 1066MHz FSB) main memory: large, slow  Up to 4GB1 Dual-Channel DDR22 SDRAM3 (667MHz) secondary memory (disk): huge, very slow  Up to 2 hard drives and 1 TB of data

4. Comp Sci 251 -- mem hierarchy 4 Goal: Illusion of Large Fast Memory Exploit two characteristics of programs: Temporal locality: programs tend to re- access recently accessed locations Spatial locality: programs tend to access neighbors of recently accessed locations

5. Comp Sci 251 -- mem hierarchy 5 Exploiting Locality Keep most recently accessed items and their neighbors in faster memory We will focus on the cache/main memory interface

6. Comp Sci 251 -- mem hierarchy 6 Terminology Cache hit  word we want to access is already in cache  transaction is fast Cache miss  word we want is not in cache  main memory access is necessary  transaction is slow

7. Comp Sci 251 -- mem hierarchy 7 Hit or Miss? Two questions on each memory access: Is the requested word in cache? Where in cache is it? Cache block contains: copy of main memory word(s) info about where word(s) came from (Note: cache block can contain >1 memory word)

8. Comp Sci 251 -- mem hierarchy 8 Direct Mapped Cache Each memory word maps to a single cache block “round robin” assignment of words to blocks (assume one-word blocks for now, byte- addressable memory) How do we tell which block a word maps to? number of cache blocks is a power of 2

9. Comp Sci 251 -- mem hierarchy 9 Direct Mapped Cache Memory Cache Memory addressdata Memory Address

10. Comp Sci 251 -- mem hierarchy 10 Direct Mapped Cache Index0 Index1 Index3 Index2 Index4 Index5 Index6 Index7 Index8 Index9 Index0 Index1 Index3 Index2 Main Memory Index Cache Memory Index

11. Comp Sci 251 -- mem hierarchy 11 Direct Mapped Cache If cache has 2 n blocks, cache block index = n bits main memory address: leftover bits are stored in cache as a tag Cache block format: V Tag Data Tag cache index00 Cache index

12. Comp Sci 251 -- mem hierarchy 12 Cache Read Operation Look up cache block indexed by low n bits of address Compare Tag in cache with Tag bits of address if valid and match: HIT  read from cache mismatch or invalid: MISS  new word + Tag is brought into cache

13. Comp Sci 251 -- mem hierarchy 13 Cache Write Operation (Problem: main memory and cache can become inconsistent) Look up cache block indexed by low n bits of address Compare Tag with high bits of address if valid and match: HIT  write cache and main memory (write-through policy) invalid or mismatch: MISS  write main memory  overwrite cache with new word + Tag

14. Comp Sci 251 -- mem hierarchy 14 Exercise Byte-addressable main memory 32-bit main memory addresses 1024KB-capacity cache; one word per cache block  256K = 2 18 cache blocks Show cache block format & address decomposition Access memory address 0x0040006c  Which cache block?  What tag bits?

15. Comp Sci 251 -- mem hierarchy 15 Cache Block Size A cache block may contain > 1 main memory word (why is this a good idea?) Example:  byte-addressable memory  4-word cache block Address: | block address |offset|00 |tag|cache index|offset|00

16. Comp Sci 251 -- mem hierarchy 16 Exercise Byte-addressable main memory 32-bit main memory addresses 1024KB-capacity cache; four words per cache block  64K=2 16 cache blocks Show cache block format & address decomposition Access memory address 0x0040006c  Which cache block?  What tag bits?

17. Comp Sci 251 -- mem hierarchy 17 Address (binary)Contents (Hex) 000000aa bb cc dd 00010000 11 00 33 001000ff ee 01 23 00110045 67 89 0a 010000bc de f0 1a 0101002a 3a 4a 5a 0110006a 7a 8a 9a 0111001b 2b 3b 4b 100000b2 b3 b4 b5 100100c1 c2 c3 c4 101000d1 d2 d3 d4 101100e1 e2 e3 e4 110000f1 f2 f3 f4 110100a1 a2 a3 a4 1110002c 3c 4c 5c 1111002d 3d 4d 5d Given main memory of 256 bytes, a memory block is one word, cache size (number of blocks ) is 8 What is the total size of the cache in bits? Memory address is m bytes long 256 bytes = 2 m bytes → m = ? You need n bits to address 8 blocks in cache. n = ? You need b bits to address 4 bytes in a word. b = ? Size of tag bits = t = m - n - b Size of cache = (1+ t + 32) x 8

18. Comp Sci 251 -- mem hierarchy 18 Address (binary)Contents (Hex) 000000aa bb cc dd 00010000 11 00 33 001000ff ee 01 23 00110045 67 89 0a 010000bc de f0 1a 0101002a 3a 4a 5a 0110006a 7a 8a 9a 0111001b 2b 3b 4b 100000b2 b3 b4 b5 100100c1 c2 c3 c4 101000d1 d2 d3 d4 101100e1 e2 e3 e4 110000f1 f2 f3 f4 110100a1 a2 a3 a4 1110002c 3c 4c 5c 1111002d 3d 4d 5d Given main memory of 256 bytes, a memory block is 2 words, cache size is 8 What is the total size of the cache in bits? Memory address is m bytes long 256 bytes = 2 m bytes → m = ? You need n bits to address 8 blocks in cache. n = ? You need b bits to address the bytes in 2 words. b = ? Size of tag bits = t = m - n – b Size of cache = (1+ t + 64) x 8

19. Comp Sci 251 -- mem hierarchy 19 Suppose a memory address is 32 bits, a memory block is 8 words and the cache size is 16K blocks. What is the total size of the cache in bytes? 32-bit Memory address Data in 8-word block 16K blocks vTag Cache