# Cache Memory Exercises. Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An.

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Cache Memory Exercises

Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An instruction lw \$t0, x or lbu \$t0, x; Determine –HIT or MISS? –What value is in \$t0?; and –Show the cache after word is brought in if needed

Address (binary) Contents (Hex) 000000aa bb cc dd 00010000 11 00 33 001000ff ee 01 23 00110045 67 89 0a 010000bc de f0 1a 0101002a 3a 4a 5a 0110006a 7a 8a 9a 0111001b 2b 3b 4b 100000b2 b3 b4 b5 100100c1 c2 c3 c4 101000d1 d2 d3 d4 101100e1 e2 e3 e4 110000f1 f2 f3 f4 110100a1 a2 a3 a4 1110002c 3c 4c 5c 1111002d 3d 4d 5d VTagdata(hex) 01011 11 00 01 10000 01 01 33 01111 11 10045 67 89 0a lbu \$t0, x # x = 001101 Question 1: cache HIT or MISS? What is in \$t0? Draw the cache after data is brought in 00 01 10 11 Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Address (binary ) Contents (Hex) 000000aa bb cc dd 00010000 11 00 33 001000ff ee 01 23 00110045 67 89 0a 010000bc de f0 1a 0101002a 3a 4a 5a 0110006a 7a 8a 9a 0111001b 2b 3b 4b 100000b2 b3 b4 b5 100100c1 c2 c3 c4 101000d1 d2 d3 d4 101100e1 e2 e3 e4 110000f1 f2 f3 f4 110100a1 a2 a3 a4 1110002c 3c 4c 5c 1111002d 3d 4d 5d VTagdata(hex) 01011 11 00 01 00000 01 01 11 000 Ffee 01 23 00000 00 lbu \$t0, x # x = 001010 Question 2: cache HIT or MISS? What is in \$t0? Draw the cache after data is brought in 00 01 10 11 Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Address (binary) Contents (Hex) 000000aa bb cc dd 00010000 11 00 33 001000ff ee 01 23 00110045 67 89 0a 010000bc de f0 1a 0101002a 3a 4a 5a 0110006a 7a 8a 9a 0111001b 2b 3b 4b 100000b2 b3 b4 b5 100100c1 c2 c3 c4 101000d1 d2 d3 d4 101100e1 e2 e3 e4 110000f1 f2 f3 f4 110100a1 a2 a3 a4 1110002c 3c 4c 5c 1111002d 3d 4d 5d VTagdata(hex) 01011 11 00 01 10000 11 00 33 01111 11 10000 00 lbu \$t0, x # x = 000111 Question 3: cache HIT or MISS? What is in \$t0? Draw the cache after data is brought in 00 01 10 11 Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Address (binary) Contents (Hex) 00000011 11 00 01 00010000 11 00 33 001000ff ee 01 23 00110045 67 89 0a 010000bc de f0 1a 0101002a 3a 4a 5a 0110006a 7a 8a 9a 0111001b 2b 3b 4b 100000b2 b3 b4 b5 100100c1 c2 c3 c4 101000d1 d2 d3 d4 101100e1 e2 e3 e4 110000f1 f2 f3 f4 110100a1 a2 a3 a4 1110002c 3c 4c 5c 1111002d 3d 4d 5d VTagdata(hex) 00111 11 00 01 10000 01 01 11 01111 11 10000 00 lbu \$t0, x # x = 010010 Question 4: cache HIT or MISS? What is in \$t0? Draw the cache after data is brought in 00 01 10 11 Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Address (binary) Contents (Hex) 000000aa bb cc dd 00010000 11 00 33 001000ff ee 01 23 00110045 67 89 0a 010000bc de f0 1a 0101002a 3a 4a 5a 0110006a 7a 8a 9a 0111001b 2b 3b 4b 100000b2 b3 b4 b5 100100c1 c2 c3 c4 101000d1 d2 d3 d4 101100e1 e2 e3 e4 110000f1 f2 f3 f4 110100a1 a2 a3 a4 1110002c 3c 4c 5c 1111002d 3d 4d 5d VTagdata(hex) 01011 11 00 01 00000 01 01 11 01111 11 00000 00 lbu \$t0, x # x = 011011 Question 5: cache HIT or MISS? What is in \$t0? Draw the cache after data is brought in 00 01 10 11 Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Cache Question II-1 Suppose: 256 bytes of memory, cache holds 4 blocks, each block is 1 word. What is the cache size? Answer: aaaaaaaa  t t t t i i o o cache: valid tag data Cache size: 1 4 32 (4+1+32)*4 bits

Cache Question II-2 Suppose: 256 bytes of memory, cache holds 8 blocks, each block is 1 word. What is the cache size? Answer: aaaaaaaa  t t t i i i o o cache: valid tag data Cache size: 1 3 32 (3+1+32)*8 bits

Question II-3 What is the cache size (total number of bits) for a cache that holds 64KB of data (block == 1 word; 2**32 bytes of memory) Answer: 64KB == 16K words; –16K = (2**4) *(2**10) = 2**14 –So 14 bits are needed for the cache index Tag size = 32 – 14 -2 = 16 bits Cache size = (1 + (32-14-2) + 32) * (2**14) = 784 K bits = 98 KB

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