331 Lec20.1Spring 2005 14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 13 Basics of Cache [Adapted from Dave Patterson’s UCB CS152.
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331 Lec20.1Spring 2005 14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 13 Basics of Cache [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]
331 Lec20.2Spring 2005 Head’s Up This week’s material l Basics of caches -Reading assignment – PH 7.2 Reminders
331 Lec20.3Spring 2005 Second Level Cache (SRAM) Review: A Typical Memory Hierarchy Control Datapath Secondary Memory (Disk) On-Chip Components RegFile Main Memory (DRAM) Data Cache Instr Cache ITLB DTLB eDRAM Speed: 1 ns 2 ns 10 ns 50 ns 1,000 ns Size: 128 B 64 KB 256 KB 4 GB TB’s Cost: highest lowest By taking advantage of the Principle of Locality: l Present the user with as much memory as is available in the cheapest technology at the access speed offered by the fastest technology.
331 Lec20.4Spring 2005 Review: Principle of Locality Temporal Locality l Keep most recently accessed data items closer to the processor Spatial Locality l Move blocks consisting of contiguous words to the upper levels Hit Time << Miss Penalty l Hit: data appears in some block in the upper level (Blk X) -Hit Rate: the fraction of accesses found in the upper level -Hit Time: Time to access the upper level = RAM access time + Time to determine hit/miss l Miss: data needs to be retrieve from a lower level block (Blk Y) -Miss Rate = 1 - (Hit Rate) -Miss Penalty: Time to replace a block in the upper level with a block from the lower level + Time to deliver this block to the processor Lower Level Memory Upper Level Memory To Processor From Processor Blk X Blk Y In general, Average Access Time: l = Hit Time + Miss Penalty x Miss Rate
331 Lec20.5Spring 2005 Review: How is the Hierarchy Managed? registers memory l by compiler (programmer?) cache main memory l by the hardware main memory disks l by the hardware and operating system (virtual memory) l by the programmer (files)
331 Lec20.6Spring 2005 Two questions to answer (in hardware): l Q1: How do we know if a data item is in the cache? l Q2: If it is, how do we find it? First method: l Direct mapped -For each item of data at the lower level, there is exactly one location in the cache where it might be (i.e., lots of items at the lower level share locations in the upper level) l Block size is one word of data l Mapping: (word address) modulo (# of words in the cache) Cache
331 Lec20.7Spring 2005 Caching: A Simple First Example 00 01 10 11 Cache 00 0001 0010 0011 010001 0110 0111 1000 100110 1011 1100 1101 111011 Main Memory Q2: How do we find it? Use low order 2 memory address bits to determine which cache block (i.e., modulo the number of blocks in the cache) TagData Q1: Is it there? Compare the cache tag to the high order 2 memory address bits to tell if the memory block is in the cache Valid
331 Lec20.8Spring 2005 Direct Mapped Cache 0123 4 3414 Consider the main memory reference string 0 1 2 3 4 3 4 14 00 Mem(0) 00 Mem(1) 00 Mem(0) 00 Mem(1) 00 Mem(2) miss hit 00 Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 014 11 14 Start with an empty cache - all blocks marked as not valid 00 Mem(1) 00 Mem(2) 00 Mem(3)
331 Lec20.9Spring 2005 Another Reference String Mapping 0404 0 404 Now consider the main memory reference string 0 4 0 4 0 4 0 4 l Ping pong effect due to conflict misses - two memory locations that map into the same cache block Start with an empty cache - all blocks marked as not valid miss 00 Mem(0) 01 4 01 Mem(4) 0 00 00 Mem(0) 01 4 00 Mem(0) 01 4 00 Mem(0) 01 4 01 Mem(4) 0 00 01 Mem(4) 0 00
331 Lec20.10Spring 2005 Sources of Cache Misses Compulsory (cold start or process migration, first reference): first access to a block l “Cold” fact of life, not a whole lot you can do about it l If you are going to run “billions” of instruction, Compulsory Misses are insignificant Conflict (collision): l Multiple memory locations mapped to the same cache location l Solution 1: increase cache size l Solution 2: increase associativity Capacity: l Cache cannot contain all blocks accessed by the program l Solution: increase cache size
331 Lec20.11Spring 2005 One word/block, cache size = 1K words MIPS Direct Mapped Cache Example Hit 20Tag 10 Index DataIndexTagValid 0 1 2. 1021 1022 1023 31 30... 13 12 11... 2 1 0 Byte offset 20 Data 32
331 Lec20.12Spring 2005 Handling Cache Misses Handling hit is trivial Handling misses needs to stall the processor Upon an instruction cache miss l Send the original PC value (current PC – 4) to the memory l Instruct main memory to perform a read and wait for the memory to complete its access l Write the cache entry, putting the data from memory in the data portion of the entry, writing the upper bits of the address (from the ALU) into the tag field, and turning the valid bit on l Restart the instruction execution at the first step, which will re-fetch the instruction, this time finding it in the cache Similar for data cache miss
331 Lec20.13Spring 2005 Handling Writes The cache and memory are inconsistent when their values (of the same data) are different A simple solution: write through l Write to both the cache and the memory at the same time l Poor performance. Every store instruction needs to stall the processor (a memory access can take 100 CPU cycles) Alternative: write back l Write to the cache; write to the memory when the cache block is replaced later.
331 Lec20.14Spring 2005 Cache Summary The Principle of Locality: l Program likely to access a relatively small portion of the address space at any instant of time -Temporal Locality: Locality in Time -Spatial Locality: Locality in Space Three Major Categories of Cache Misses: l Compulsory Misses: sad facts of life. Example: cold start misses l Conflict Misses: increase cache size and/or associativity Nightmare Scenario: ping pong effect! l Capacity Misses: increase cache size Cache Design Space l total size, block size, associativity (replacement policy) l write-hit policy (write-through, write-back) l write-miss policy (write allocate, write buffers)
331 Lec20.15Spring 2005 The off-chip interconnect and memory architecture can affect overall system performance in dramatic ways. Memory Systems that Support Caches CPU Cache Memory bus One word wide organization (one word wide bus and one word wide memory) Assume 1. 1 clock cycle (2 ns) to send the address 2. 25 clock cycles (50 ns) for DRAM cycle time, 8 clock cycles (16 ns) access time 3. 1 clock cycle (2ns) to return a word of data Memory-Bus to Cache bandwidth number of bytes accessed from memory and transferred to cache/CPU per clock cycle 32-bit data & 32-bit addr per cycle on-chip
331 Lec20.16Spring 2005 One Word Wide Memory Organization CPU Cache Memory bus on-chip If the block size is one word, then for a memory access due to a cache miss, the pipeline will have to stall the number of cycles required to return one data word from memory cycle to send address cycles to read DRAM cycle to return data total clock cycles miss penalty Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock 1 25 1 27 4/27 = 0.148
331 Lec20.17Spring 2005 One Word Wide Memory Organization, con’t CPU Cache Memory bus on-chip What if the block size is four words? cycle to send 1 st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock 25 cycles 1 4 x 25 = 100 1 102 (4 x 4)/102 = 0.157
331 Lec20.18Spring 2005 Interleaved Memory Organization For a block size of four words cycle to send 1 st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty CPU Cache Memory bank 1 bus on-chip Memory bank 0 Memory bank 2 Memory bank 3 Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock 25 cycles (4 x 4)/30 = 0.533 1 25 + 3 = 28 1 30
331 Lec20.19Spring 2005 DRAM Memory System Summary Its important to match the cache characteristics l caches access one block at a time (usually more than one word) with the DRAM characteristics l use DRAMs that support fast multiple word accesses, preferably ones that match the block size of the cache with the memory-bus characteristics l make sure the memory-bus can support the DRAM access rates and patterns l with the goal of increasing the Memory-Bus to Cache bandwidth