1. 2010 IEEE Device Research Conference, June 21-23, Notre Dame, Indiana
III-V FET Channel Designs for High Current Densities and Thin Inversion Layers
Mark Rodwell University of California, Santa Barbara
Coauthors:
W. Frensley: University of Texas, Dallas
S. Steiger, S. Lee, Y. Tan, G. Hegde, G. Klimek Network for Computational Nanotechnology, Purdue University
E. Chagarov, L. Wang, P. Asbeck, A. Kummel, University of California, San Diego
T. Boykin University of Alabama, Huntsville J. N. Schulman The Aerospace Corporation, El Segundo, CA.
Acknowledgements: Herb Kroemer (UCSB), Bobby Brar (Teledyne) Art Gossard (UCSB), John Albrecht (DARPA)
, fax

2. Thin, high current density III-V FET channels
InGaAs, InAs FETs THz & VLSI need high current low m*→ high velocities
FET scaling for speed requires increased charge density low m* →low charge density
Density of states bottleneck (Solomon & Laux IEDM 2001) → For < 0.6 nm EOT, silicon beats III-Vs
Open the bottle !
low transport mass → high vcarrier multiple valleys or anistropic valleys → high DOS Use the L valleys.

3. Goal: double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays → keep constant all resistances, voltages, currents
Simple FET Scaling
gate-source, gate-drain fringing capacitances: fF/mm
must increase gate capacitance/area
must reduce gate length

4. FET Scaling Laws laws in constant-voltage limit: FET parameter change
Changes required to double device / circuit bandwidth.
laws in constant-voltage limit:
FET parameter
change
gate length
decrease 2:1
current density (mA/mm), gm (mS/mm)
increase 2:1
channel 2DEG electron density
electron mass in transport direction
constant
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
decrease 4:1
Current densities should double Charge densities must double

5. Semiconductor Capacitances Must Also Scale

6. Calculating Current: Ballistic Limit
Do we get highest current with high or low mass ?

7. Drive current versus mass, # valleys, and EOT
InGaAs MOSFETs: superior Id to Si at large EOT. InGaAs MOSFETs: inferior Id to Si at small EOT.
Solomon / Laux Density-of-States-Bottleneck → III-V loses to Si.

8. Transit delay versus mass, # valleys, and EOT
Low m* gives lowest transit time, lowest Cgs at any EOT.

9. Low effective mass also impairs vertical scaling
Shallow electron distribution needed for high Id, high gm / Gds ratio, low drain-induced barrier lowering.
Energy of Lth well state
For thin wells,
only 1st state can be populated.
For very thin wells,
1st state approaches L-valley.
Only one vertical state in well. Minimum ~ 3 nm well thickness.
→ Hard to scale below nm Lg.

10. III-V Band Properties, normal {100} Wafer

11. Consider instead: valleys in {111} Wafer

12. Valley in {111} wafer: with quantization in thin wells

13. {111} G-L FET: Candidate Channel Materials

14. Standard III-V FET: G valley in [100] orientation
3 nm GaAs well AlSb barriers
G=0 eV L=177 meV X[100]= 264 meV X[010] = 337 meV

15. 1st Approach: Use both G and L valleys in [111]
2.3 nm GaAs well AlSb barriers [111] orientation
G= 41 meV L[111] (1)= 0 meV L[111] (2)= 84 meV L[111] , etc. =175 meV X=288 meV

16. Combined G-L wells in {111} orientation vs. Si
combined (G -L) transport
2 nm GaAs G /L well→ g =2, m*/m0=0.07
4 nm GaSb G /L well→ mG*/m0=0.039, mL,t*/m0=0.1

17. 2nd Approach: Use L valleys in Stacked Wells
Three nm GaAs wells 0.66 nm AlSb barriers [111] orientation
L[111](1) = 0 meV L[111](2)= 61 meV L[111](3)= 99 meV G=338 meV L[111], etc =232 meV X=284 meV

18. Increase in Cdos with 2 and 3 wells

19. 3 High Current Density (111) GaAs/AlSb Designs

20. Nonparabolic bands reduce bound state energies
Concerns
Nonparabolic bands reduce bound state energies
Failure of effective mass approximation:1-2 nm wells
1-2 monolayer fluctuations in growth → scattering→ collapse in mobility

21. Purdue Confirmation

22. Steiger, Klimeck, Boykin Ryu, Lee, Hegde, Tan
Purdue Confirmation

23. 1-D FET array = 2-D FET with high transverse mass
1-D Array FET
Weak coupling → narrow transverse-mode energy distribution→ high density of states

24. 3rd Approach: High Current Density L-Valley MQW FINFETs

25. 4th Approach: {110} Orientation→ Anisotropic Bands
transport

26. Anisotropic bands, e.g. {110}
Transport in {110} oriented L valleys

27. THz FET scaling: with & without increased DOS
Gate length nm 50 35 25 18 13 9
Gate barrier EOT
1.2
0.83
0.58
0.41
0.29
0.21
well thickness
8.0
5.7
4.0
2.8
2.0
1.4
S/D resistance
W-mm
210
150
100 74 53 37
effective mass
*m0
0.05
0.08
# band minima canonical fixed DOS stepped # 1 2
4 1 3

28. Scaled FET performance: fixed vs. increasing DOSft
fmax
SCFL divider speed
mA/mm→ VLSI metric
Increased density of states needed for high drive current, fast 16, 11, 8 nm nodes

29. 10 nm / 3 THz III-V FETs: Challenges & Solutions
gate dielectric: decrease EOT 2:1
To double the bandwidth:
channel: keep same velocity, but thin channel 2:1 increase density of states 2:1
S/D access regions: decrease resistivity 2:1
S/D regrowth
Wistey et al Singisetti et al

30. (end)

31. Purdue Confirmation

32. MOSFET Scaling Laws

33. 2.0 nm GaAs well, AlAs barriers, on {111} GaAs

34. GaSb well, AlSb barriers, on {110} GaSb