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MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4 WP1: Giuliana GangemiWP2: André Juge WP3: Wilmar HeuvelmanWP4:

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Presentation on theme: "MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4 WP1: Giuliana GangemiWP2: André Juge WP3: Wilmar HeuvelmanWP4:"— Presentation transcript:

1 MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4 WP1: Giuliana GangemiWP2: André Juge WP3: Wilmar HeuvelmanWP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: June 22, 2010 (09.30 - 17.00 hrs) Review period: 2009-03-01 : 2010-02-28

2 CONFIDENTIAL 2 MODERN 1st Year Review June 22, 2010 Agenda General information (JvG) –Objectives –Consortium –Resources planned and used –Overview of deliverables and milestones status –Cooperation, dissemination and exploitation –Project management: progress, funding problems and amendments –Other issues, Q&A For WP1 (GG), WP2 (AJ), WP3 (WH), WP4 (DP) and WP5 (LV) –Relationship between workpackages –Progress, highlights and lowlights –Technical status and achievements of deliverables (incl. changes) –Cooperation –Dissemination (publications, patents), exploitation –Other issues, Q&A

3 CONFIDENTIAL 3 MODERN 1st Year Review June 22, 2010 Objectives The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. Specifically, the main goals of the project are:  Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures.  Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. oReliability, noise, EMC/EMI. oTiming, power and yield.  Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.  Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys)

4 CONFIDENTIAL 4 MODERN 1st Year Review June 22, 2010 Consortium The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. 9 Countries28 Partners

5 CONFIDENTIAL 5 MODERN 1st Year Review June 22, 2010 Resources planned and used

6 CONFIDENTIAL 6 MODERN 1st Year Review June 22, 2010 Overview of deliverables and milestones status (1)

7 CONFIDENTIAL 7 MODERN 1st Year Review June 22, 2010 Overview of deliverables and milestones status (2)

8 CONFIDENTIAL 8 MODERN 1st Year Review June 22, 2010 Overview of deliverables and milestones status (3)

9 CONFIDENTIAL 9 MODERN 1st Year Review June 22, 2010 Cooperation, dissemination and exploitation

10 CONFIDENTIAL 10 MODERN 1st Year Review June 22, 2010 Project management: progress, funding problems and amendments

11 CONFIDENTIAL 11 MODERN 1st Year Review June 22, 2010 Other issues Q&A

12 CONFIDENTIAL 12 MODERN 1st Year Review June 22, 2010 WP1: Relationship between workpackages

13 CONFIDENTIAL 13 MODERN 1st Year Review June 22, 2010 WP1: Progress, highlights and lowlights Task T1.x: Task name Partners (underlined task leader) : Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions.

14 CONFIDENTIAL 14 MODERN 1st Year Review June 22, 2010 WP1: Technical status and achievements of deliverables (incl. changes)

15 CONFIDENTIAL 15 MODERN 1st Year Review June 22, 2010 WP1: Cooperation WP leader: ST-I If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when)

16 CONFIDENTIAL 16 MODERN 1st Year Review June 22, 2010 WP1: Dissemination (publications, patents), exploitation

17 CONFIDENTIAL 17 MODERN 1st Year Review June 22, 2010 WP1: Other issues, Q&A

18 CONFIDENTIAL 18 MODERN 1st Year Review June 22, 2010 WP2: Relationship between workpackages

19 CONFIDENTIAL 19 MODERN 1st Year Review June 22, 2010 Task T2.x: Task name Partners (underlined task leader) : Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. WP2: Progress, high- and lowlights

20 CONFIDENTIAL 20 MODERN 1st Year Review June 22, 2010 WP2: Technical status and achievements of deliverables (incl. changes)

21 CONFIDENTIAL 21 MODERN 1st Year Review June 22, 2010 WP2: Cooperation WP leader: STF2 If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when)

22 CONFIDENTIAL 22 MODERN 1st Year Review June 22, 2010 WP2: Dissemination (publications, patents), exploitation

23 CONFIDENTIAL 23 MODERN 1st Year Review June 22, 2010 WP2: Other issues, Q&A

24 CONFIDENTIAL 24 MODERN 1st Year Review June 22, 2010 WP3: Relationship between workpackages

25 CONFIDENTIAL 25 MODERN 1st Year Review June 22, 2010 Task T3.x: Task name Partners (underlined task leader) : Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. WP3: Progress, high- and lowlights

26 CONFIDENTIAL 26 MODERN 1st Year Review June 22, 2010 WP3: Technical status and achievements of deliverables (incl. changes)

27 CONFIDENTIAL 27 MODERN 1st Year Review June 22, 2010 WP3: Cooperation WP leader: NXP If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when)

28 CONFIDENTIAL 28 MODERN 1st Year Review June 22, 2010 WP3: Dissemination (publications, patents), exploitation

29 CONFIDENTIAL 29 MODERN 1st Year Review June 22, 2010 WP3: Other issues, Q&A

30 CONFIDENTIAL 30 MODERN 1st Year Review June 22, 2010 WP4: Relationship between workpackages

31 CONFIDENTIAL 31 MODERN 1st Year Review June 22, 2010 Task T4.x: Task name Partners (underlined task leader) : Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. WP4: Progress, high- and lowlights

32 CONFIDENTIAL 32 MODERN 1st Year Review June 22, 2010 WP4: Technical status and achievements of deliverables (incl. changes)

33 CONFIDENTIAL 33 MODERN 1st Year Review June 22, 2010 WP4: Cooperation WP leader: ST-I If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when)

34 CONFIDENTIAL 34 MODERN 1st Year Review June 22, 2010 WP4: Dissemination (publications, patents), exploitation

35 CONFIDENTIAL 35 MODERN 1st Year Review June 22, 2010 WP4: Other issues, Q&A

36 CONFIDENTIAL 36 MODERN 1st Year Review June 22, 2010 WP5: Relationship between workpackages

37 CONFIDENTIAL 37 MODERN 1st Year Review June 22, 2010 WP5: Test structures and demonstrators 3 tasks: “test structures”, “hw demonstrators”, “sw demonstrators” Strong dependencies from WP 2,3,4: -close the loop also directly to each WP (efficiency) -‘light’ structure for WP5 -in depth result analysis done in respective WP -WP5 deliverables: list and description of activities and result summary. First year: 3 deliverables (one per task) released on schedule major results and technical achievements discussed in the following WP5: Progress, high- and lowlights

38 CONFIDENTIAL 38 MODERN 1st Year Review June 22, 2010 Task T5.1: Test structures for PV analysis: design, implementation and characterization Partners: AMS, NMX, STF2, TUGI First year goals: -critical review of state of the art test structure for inter and intra die variability -possible improvements All task partners involved in D.5.1.1 “Review of Test Structure State of the Art and First Results on Inter-Die Variability and Matching Characterization on Available Structures in Different Technology Nodes” Technology involved: 0.35um HVCMOS working up to 120V (AMS) 45nm CMOS (STM) NonVolatileMemory 1.8V (NMX) partner complementarity mismatch WP5: T5.1 Technical status, D5.1.1 achievements

39 CONFIDENTIAL 39 MODERN 1st Year Review June 22, 2010 AMS-TUGI standard and Kelvin probe measurement technique Accuracy vs. pad-count

40 CONFIDENTIAL 40 MODERN 1st Year Review June 22, 2010 AMS-TUGI Transistor (W/L=40/0.5 um/um) threshold voltage offset ΔVTH=VTH1-VTH2 lot-to-lotwafer-to-wafer

41 CONFIDENTIAL 41 MODERN 1st Year Review June 22, 2010 STF2 Classical vs. Kelvin type Mismatch Test-Structures Biasing algorithm and results

42 CONFIDENTIAL 42 MODERN 1st Year Review June 22, 2010 NMX: Combined Mismatch Test-Structures Same structure for mosfets and poly-gate resistance mismatch (possible detection: layout impact, systematic/stochastic effects, process impact) dummy on mos1 and mos2 dummy on mos2 only L of mos2 slightly changes

43 CONFIDENTIAL 43 MODERN 1st Year Review June 22, 2010 Task T5.2: Demonstrator: design, implementation and characterization Partners: IFXA, NXP, UPC, THL, TMPO, LETI, TUGI, AMS First year goals: general preparatory activities for hw demonstrators and basic concept verification for noise, compensation and other test-chip architectures. IFXA and NXP partners involved in D.5.2.1 “Basic concept verification of noise, compensation, test chip architectures”. Other partners: -AMS and TUG: preparatory definition of benchmark cases and tools for PV aware and lifetime-critical device models of WP2 -LETI: preliminary steps to implement on silicon (32 nm) a Local Adaptive Voltage and Frequency Scaling (LAVFS) architecture based on WP3 and WP4 developments; principle Vdd-Hopping' technique, major activities on analog sub-bloks for actuators, PVT sensors and timing slack monitors in 32 nm -UPC: preparatory activities to design single supply voltage level shifters and regular digital structures from WP4 -TIEMPO activities will start in the second year -THL activities in the next year WP5: T5.2 Technical status, D5.2.1 achievements

44 CONFIDENTIAL 44 MODERN 1st Year Review June 22, 2010 IFXA: Monitor & Control (compensation) and test- chip architectures TC1: verification of aging simulations of WP3-T3.3 Two stages Miller compensated OP-AMP + stress&test measurement concept for fast transients (us….100s) Preliminary results: aging mainly generates offset and transient relaxation effects significantly impact the generated offset until a steady state is reached in the range of several seconds

45 CONFIDENTIAL 45 MODERN 1st Year Review June 22, 2010 IFXA: Monitor & Control (compensation) and test- chip architectures TC2: Monitor & control concepts under development -array of matched devices that are biased with equal stress conditions -switch degradation monitor by ring-oscillators (degradation of resistance will decrease the frequency) -ADC concept including error correction Preparatory steps for TC3 VCO test-bench / disengageable VCO (ring aged acting as PLL) TC2 layouts and ring concepts

46 CONFIDENTIAL 46 MODERN 1st Year Review June 22, 2010 NXP: Substrate Noise Previous work (MEDEA+ Robin): measured noise by sensors for different protections to be improved by deembedding techniques New test chip “Neptune 5”, 65nm CMOS Features: -complex radio front ends as victims -digital IO buffers as aggressors -various grounding strategies -impact of different seal rings (analogue and digital GNDs) contribution to the substrate noise coupling -metal and FIB options sensor

47 CONFIDENTIAL 47 MODERN 1st Year Review June 22, 2010 Task T5.3: Software demonstrator and tool prototype Partners: SNPS, NXP, ST-I, THL Project goals: Demonstrations of TCAD and CAD prototype software tools to asses the methodologies and algorithms coming out from WP2/3/4. D5.3.1 “Report on Software prototype implementation of Model Order Reduction for Multiple Input Multiple Output systems of R, RC, RCL” by NXP only. Other partners: -ST-I activity from 2 nd year -Thales: working on a pedestrian detection application to be used on top of the architecture developed in T4.3 to test the repairing capabilities with the fault scenarios from T4.5. -SNPS: preparation works (tool/methodology development for Sentaurus device, definition of benchmark structures, preparation of hardware data, testing) for next year activity; implementation of the Green’s Function method for geometrical fluctuation in 3D. Strong links with task T2.2. WP5: T5.3 Technical status, D5.3.1 achievements

48 CONFIDENTIAL 48 MODERN 1st Year Review June 22, 2010 NXP: Model Order Reduction Focus: Parametrized MOR that preserve sub-structure, accuracy and stability (passivity) SparseMA: the proposed model approximation

49 CONFIDENTIAL 49 MODERN 1st Year Review June 22, 2010 WP5: Cooperation WP leader: NMX -Coordination among WP leaders in general meetings and separate phone calls -Task on-line meetings with participation of WP4 leader: T5.1 January 2010, T5.2 December 2009, -Phone calls and emails contacts for the “day by day” activities -Dedicated phone calls and email for the “CMP” silicon (see later) -Strongest cooperation is within “national clusters” -LIRMM will partecipate to this WP through the cooperative activities they are involved in the other WPs. LIRMM is planning, for the second year, the design, in close cooperation with CEA/LETI, of a platform based on an array of processing elements, called Smart ModEm Processors (SMEP), interconnected by a Network-on-Chip

50 CONFIDENTIAL 50 MODERN 1st Year Review June 22, 2010 WP5: Dissemination (publications, patents), exploitation NMX: L. Bortesi, L. Vendrame, G. Fontana,”Combined test structure for systematic and stochastic Mosfets and gate resistance process variation assessment”, IEEE ICMTS 2010, pp227-230. ??? LIRMM :MPSoC plateform has been validated by simulation, first results presented at the DATE conference ???? ifat iprs2010 IFXA: F. Chouard, Ch. Werner, M. Fulde, D. Schmitt-Landsiedel, “A Test Concept For Circuit Level Aging Demonstrated By A Differential Amplifier”, IEEE IRPS 2010 pp.826-830

51 CONFIDENTIAL 51 MODERN 1st Year Review June 22, 2010 WP5: Other issues, Q&A Part on the silicon (partners linked to the French cluster) will be spinned using CMP facilities: - plans of silicon runs are not under control of the partners - “additional” external schedule to be carefully taken into account. - risk assessment delivered (D.6.1.3) - continuous monitoring is ongoing - safer solution: 65nm CMOS technology (not very aggressive but useful for concept and methodologies proof)

52 CONFIDENTIAL 52 MODERN 1st Year Review June 22, 2010 WP5: Technical status and achievements of deliverables (incl. changes)

53 CONFIDENTIAL 53 MODERN 1st Year Review June 22, 2010


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