1. Integrated Regulation for Energy- Efficient Digital Circuits Elad Alon 1 and Mark Horowitz 2 1 UC Berkeley 2 Stanford University

2. Technology (μm) Scaling and Supply Impedance CMOS scaling led to lower supply voltages and constant (or increasing) power consumption Forces drastic drop in supply impedance V dd ↓, I dd ↑  |Z required | ↓↓ Today’s chips: |Z required | ≈ 1 m Ω! Hard to achieve across a broad frequency range Required Impedance (Ω) Impedance Requirements of High-Performance Processors

3. Power Distribution and Regulation Significant resources spent to meet impedance requirement Active regulation can be used to reduce impedance E.g., Active/switched decoupling But, these regulators increase total power Prevents adoption in today’s power-limited chips

4. Power-Neutral Regulation Gate delay depends on V dd So V dd needs to be greater than some V min Supply variations force higher nominal voltage Causes extra power dissipation Goal: make regulator power less than power recovered from lower noise V min V nom V dd

5. Outline Regulator Topology Regulator Design Experimental Verification Conclusions

6. Linear Regulators V dd Load V reg Chip + - + - V ref Series Regulator Load V reg Chip + - + - V ref Shunt Regulator V dd

7. Series Regulator Efficiency Clearly won’t meet efficiency goal: Regulator doesn’t really change noise on V dd So still need same margin But added an extra V drop from variable resistor… + - V ref Load V dd V reg V dd V reg V drop Noise

8. Shunt Regulator Efficiency Regulator can only pull current out of supply Need to burn significant static current to counter noise in both directions Again, clearly inefficient Need to allow shunt to deliver energy to the load Not just dissipate it Load + - V ref V reg I shunt I total I load 0 max(I noise )

9. Push-Pull Shunt Regulator Use an additional, “shunt” supply to push current into V reg Regulator capable of countering large variations But regulator loss set mostly by average variation Similar to Active Clamp * for board VRMs Build on previous work to improve on-die impedance Load + - V ref V reg V shunt + - I push I pull I push I load 0 I pull *A.M. Wu and S.R. Sanders, “An Active Clamp Circuit for Voltage Regulation Module (VRM) Applications,” Transactions on Power Electronics. Sept. 2001.

10. Outline Regulator Topology Regulator Design Shunt Supply Network Minimizing Static Power Experimental Verification Conclusions

11. Regulator Design Challenges V shunt is not free Takes resources away from main supply Increases loss Load + - V ref V reg V shunt + - I push I pull Need to minimize quiescent output current Otherwise regulator too inefficient Need GHz bandwidth feedback path With minimum feedback circuit power Output stage in particular is challenging

12. Shunt Supply Resource Allocation Finite number of pins, metal lines for power Need to allocate resources between main and shunt supplies For resistive losses: If ensure that V shunt only handles transients Resistive losses of main supply not heavily affected

13. Quiescent Output Current Went to push-pull topology to minimize quiescent current But many designs have significant I static To ensure output devices are off when V reg is quiet Use non-linear switching to control the output stage V ref V gn V gp V shunt V reg I static

14. Comparator Feedback with Dead-Band Use comparators in feedback path to generate full-swing drive signals To avoid limit cycle: Offset thresholds to create dead-band

15. Output Stage Design Needs good supply rejection V shunt will be noisy Needs to burn minimal static power To meet efficiency goal Requirements on output stage: Needs low t d,on To maintain voltage- positioned response

16. Replica Biased Output Stage Replica loop sets gate bias (V bias ) Minimal current spent in feedback amplifier for efficiency High impedance amp – add buffer between V bias and switching node

17. Switched Source Follower Buffer Source follower M p_sf used to isolate V bias Turned on only when pushing current But, waiting for I sf to charge V gn too slow M p_up turned on during transition

18. Outline Regulator Topology Regulator Design Experimental Verification Conclusions

19. Test-Chip Details 65nm SOI AMD test-chip Regulator uses same power distribution scheme as processor With reallocation for V shunt On-chip noise generator and perf. monitor for testing Regulator Circuits Scan/Config. Processor

20. Measured Results Regulator reduces broadband noise by ~30% Total power dissipation actually reduced by up to ~1.4%

21. Impedance with Faster Process Process was in development Low device f t Measurement matches simulation with slower devices Expect to reach ~50% noise and ~4% power reduction in production process with higher f t

22. Outline Regulator Topology Regulator Design Experimental Verification Conclusions

23. To be adopted, on-chip regulation must not increase total power Can in fact build power-neutral regulator Push-pull topology with second supply Switched source-follower output stage Measured 30% noise reduction with no power penalty In fact, reduced power by ~1.4%

24. Acknowledgements This work was funded in part by C2S2 (www.c2s2.org) AMD Sunnyvale Design Center