1. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 1 Part III The Arithmetic/Logic Unit

2. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 2 III The Arithmetic/Logic Unit Topics in This Part Chapter 9 Number Representation Chapter 10 Adders and Simple ALUs Chapter 11 Multipliers and Dividers Chapter 12 Floating-Point Arithmetic Overview of computer arithmetic and ALU design: Review representation methods for signed integers Discuss algorithms & hardware for arithmetic ops Consider floating-point representation & arithmetic

3. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 3 11 Multipliers and Dividers Modern processors perform many multiplications & divisions: Encryption, image compression, graphic rendering Hardware, vs programmed shift-add/sub, algorithms Topics in This Chapter 11.1 Shift-Add Multiplication 11.2 Hardware Multipliers 11.3 Programmed Multiplication 11.4 Shift-Subtract Division 11.5 Hardware Dividers 11.6 Programmed Division

4. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 4 11.1 Shift-Add Multiplication Figure 11.1 Multiplication of 4-bit numbers in dot notation. z (j+1) = (z (j) + y j x 2 k ) 2 –1 with z (0) = 0 and z (k) = z |––– add –––| |–– shift right ––|

5. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 5 Binary and Decimal Multiplication Figure 11.2 Step-by-step multiplication examples for 4-digit unsigned numbers. Position 7 6 5 4 3 2 1 0Position 7 6 5 4 3 2 1 0========================= x2 4 1 0 1 0x10 4 3 5 2 8 y 0 0 1 1y 4 0 6 7========================= z (0) 0 0 0 0 +y 0 x2 4 1 0 1 0+y 0 x10 4 2 4 6 9 6–––––––––––––––––––––––––– 2z (1) 0 1 0 1 010z (1) 2 4 6 9 6 z (1) 0 1 0 1 0z (1) 0 2 4 6 9 6 +y 1 x2 4 1 0 1 0+y 1 x10 4 2 1 1 6 8–––––––––––––––––––––––––– 2z (2) 0 1 1 1 1 010z (2) 2 3 6 3 7 6 z (2) 0 1 1 1 1 0z (2) 2 3 6 3 7 6 +y 2 x2 4 0 0 0 0+y 2 x10 4 0 0 0 0 0–––––––––––––––––––––––––– 2z (3) 0 0 1 1 1 1 010z (3) 0 2 3 6 3 7 6 z (3) 0 0 1 1 1 1 0z (3) 0 2 3 6 3 7 6 +y 3 x2 4 0 0 0 0+y 3 x10 4 1 4 1 1 2–––––––––––––––––––––––––– 2z (4) 0 0 0 1 1 1 1 010z (4) 1 4 3 4 8 3 7 6 z (4) 0 0 0 1 1 1 1 0z (4) 1 4 3 4 8 3 7 6========================= Example 11.1

6. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 6 Two’s-Complement Multiplication Figure 11.3 Step-by-step multiplication examples for 2’s-complement numbers. Position 7 6 5 4 3 2 1 0Position 7 6 5 4 3 2 1 0========================= x2 4 1 0 1 0x2 4 1 0 1 0 y 0 0 1 1y 1 0 1 1========================= z (0) 0 0 0 0 0 +y 0 x2 4 1 1 0 1 0+y 0 x2 4 1 1 0 1 0–––––––––––––––––––––––––– 2z (1) 1 1 0 1 02z (1) 1 1 0 1 0 z (1) 1 1 1 0 1 0z (1) 1 1 1 0 1 0 +y 1 x2 4 1 1 0 1 0+y 1 x2 4 1 1 0 1 0–––––––––––––––––––––––––– 2z (2) 1 0 1 1 1 02z (2) 1 0 1 1 1 0 z (2) 1 1 0 1 1 1 0z (2) 1 1 0 1 1 1 0 +y 2 x2 4 0 0 0 0 0+y 2 x2 4 0 0 0 0 0–––––––––––––––––––––––––– 2z (3) 1 1 0 1 1 1 02z (3) 1 1 0 1 1 1 0 z (3) 1 1 1 0 1 1 1 0z (3) 1 1 1 0 1 1 1 0 +(–y 3 x2 4 )0 0 0 0 0+(–y 3 x2 4 )0 0 1 1 0–––––––––––––––––––––––––– 2z (4) 1 1 1 0 1 1 1 02z (4) 0 0 0 1 1 1 1 0 z (4) 1 1 1 0 1 1 1 0z (4) 0 0 0 1 1 1 1 0========================= Example 11.2

7. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 7 11.2 Hardware Multipliers Figure 11.4 Hardware multiplier based on the shift-add algorithm.

8. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 8 The Shift Part of Shift-Add Figure11.5 Shifting incorporated in the connections to the partial product register rather than as a separate phase.

9. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 9 High-Radix Multipliers Radix-4 multiplication in dot notation. z (j+1) = (z (j) + y j x 2 k ) 4 –1 with z (0) = 0 and z (k/2) = z |––– add –––| |–– shift right ––| Assume k even

10. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 10 Tree Multipliers Figure 11.6 Schematic diagram for full/partial-tree multipliers.

11. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 11 Array Multipliers Figure 11.7 Array multiplier for 4-bit unsigned operands.

12. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 12 11.3 Programmed Multiplication MiniMIPS instructions related to multiplication mult $s0,$s1# set Hi,Lo to ($s0)  ($s1); signed multu $s2,$s3# set Hi,Lo to ($s2)  ($s3); unsigned mfhi $t0# set $t0 to (Hi) mflo $t1# set $t1 to (Lo) Finding the 32-bit product of 32-bit integers in MiniMIPS Multiply; result will be obtained in Hi,Lo For unsigned multiplication: Hi should be all-0s and Lo holds the 32-bit result For signed multiplication: Hi should be all-0s or all-1s, depending on the sign bit of Lo Example 11.3

13. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 13 Figure 11.8 Register usage for programmed multiplication superimposed on the block diagram for a hardware multiplier. Multiplication When There Is No Multiply Instruction Example 11.4 (MiniMIPS shift-add program for multiplication)

14. October 2005Michael Frank, FAMU-FSU College of Engineering 14 MIPS Assembly Code for this Multiplication Algorithm shamu:move$v0,$zero# Initialize Hi to 0 move$v1,$zero# Initialize Lo to 0 addi$t2,$zero,32# Initialize repetition counter to 32. mloop:move$t0,$zero# Loop: Initialize carry to 0. andi$t1,$a1,1# LSB of multiplier to shift out. srl$a1,$a1,1# Shift the multiplier right. beqz$t1,no_add# If bit shifted out was not 0, then addu$v0,$v0,$a0#add multiplicand into Hi word, sltu$t0,$v0,$a0#and remember the carry out. no_add:andi$t1,$v0,1# LSB of Hi word to shift out. srl$v0,$v0,1# Shift Hi word of product right. sll$t0,$t0,31# Shift carry left to position 31. or$v0,$t0,$v0# OR the carry into the Hi word. srl$v1,$v1,1# Shift Lo word of product right. sll$t1,$t1,31# Shift bit left to position 31. or$v1,$t1,$v1# OR the bit into the Lo word. addi$t2,$t2,-1# Decrement loop counter. bnez$t2,mloop# Continue while counter is nonzero. jr$ra# Return product=($v0,$v1) to caller.

15. October 2005Michael Frank, FAMU-FSU College of Engineering 15 C language equivalent unsigned long shamu(unsigned int mcand, unsigned int mer) { unsigned int Hi,Lo,carry,bit,counter; Lo = Hi = 0; /* Initialize product registers to 0. */ counter = 32;/* Initialize repetition counter to 32. */ do {/* Repeat the following loop: */ carry = 0;/* Initialize carry-out bit to 0. */ bit = mer & 1; /* t1 := LSB of m'er. */ mer >>= 1;/* Shift m'er right by 1. */ if (bit) {/* If low bit of multiplier was 1, then */ Hi += mcand; /* Add mcand into Hi */ carry = (Hi < mcand);/* Carry out from add */ }/* END IF. */ bit = Hi & 1;/* LSB of Hi */ Hi = (carry > 1);/* Shift carry into Hi */ Lo = (bit > 1);/* Shift into Lo */ counter--;/* Decrement counter. */ } while (counter > 0); return ((unsigned long)Hi)<<32 & Lo;/* Return 64-bit result. */ } /* END FUNCTION shamu() */

16. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 16 11.4 Shift-Subtract Division Figure11.9 Division of an 8-bit number by a 4-bit number in dot notation. z (j) = 2z (j  1)  y k  j x 2 k with z (0) = z and z (k) = 2 k s | shift | |–– subtract ––|

17. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 17 Integer and Fractional Unsigned Division Figure 11.10 Division examples for binary integers and decimal fractions. Position 7 6 5 4 3 2 1 0Position –1 –2 –3 –4 –5 –6 –7 –8 =================================================== z 0 1 1 1 0 1 0 1z. 1 4 3 5 1 5 0 2 x2 4 1 0 1 0x. 4 0 6 7 =================================================== z (0) 0 1 1 1 0 1 0 1 z (0). 1 4 3 5 1 5 0 2 2z (0) 0 1 1 1 0 1 0 1 10z (0) 1. 4 3 5 1 5 0 2 –y 3 x2 4 1 0 1 0 y 3 =1–y –1 x1. 2 2 0 1 y –1 =3 ––––––––––––––––––––––––––––––––––––––––––––––––––––– z (1) 0 1 0 0 1 0 1z (1). 2 1 5 0 5 0 2 2z (1) 0 1 0 0 1 0 110z (1) 2. 1 5 0 5 0 2 –y 2 x2 4 0 0 0 0 y 2 =0–y –2 x2. 0 3 3 5 y –2 =5 ––––––––––––––––––––––––––––––––––––––––––––––––––––– z (2) 1 0 0 1 0 1z (2). 1 1 7 0 0 2 2z (2) 1 0 0 1 0 110z (2) 1. 1 7 0 0 2 –y 1 x2 4 1 0 1 0 y 1 =1–y –3 x0. 8 1 3 4 y –3 =2 ––––––––––––––––––––––––––––––––––––––––––––––––––––– z (3) 1 0 0 0 1 z (3). 3 5 6 6 2 2z (3) 1 0 0 0 1 10z (3) 3. 5 6 6 2 –y 0 x2 4 1 0 1 0 y 0 =1–y –4 x3. 2 5 3 6 y –4 =8 ––––––––––––––––––––––––––––––––––––––––––––––––––––– z (4) 0 1 1 1 z (4). 3 1 2 6 s 0 1 1 1s. 0 0 0 0 3 1 2 6 y 1 0 1 1y. 3 5 2 8 =================================================== Example 11.5

18. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 18 Division with Same-Width Operands Figure 11.11 Division examples for 4/4-digit binary integers and fractions. Position 7 6 5 4 3 2 1 0Position –1 –2 –3 –4 –5 –6 –7 –8 =================================================== z 0 0 0 0 1 1 0 1z. 0 1 0 1 x2 4 0 1 0 1x. 1 1 0 1 =================================================== z (0) 0 0 0 0 1 1 0 1 z (0). 0 1 0 1 2z (0) 0 0 0 1 1 0 1 2z (0) 0. 1 0 1 0 –y 3 x2 4 0 0 0 0 y 3 =0–y –1 x0. 0 0 0 0 y –1 =0 ––––––––––––––––––––––––––––––––––––––––––––––––––––– z (1) 0 0 0 1 1 0 1z (1). 1 0 1 0 2z (1) 0 0 1 1 0 12z (1) 1. 0 1 0 0 –y 2 x2 4 0 0 0 0 y 2 =0–y –2 x0. 1 1 0 1 y –2 =1 ––––––––––––––––––––––––––––––––––––––––––––––––––––– z (2) 0 0 1 1 0 1z (2). 0 1 1 1 2z (2) 0 1 1 0 12z (2) 0. 1 1 1 0 –y 1 x2 4 0 1 0 1 y 1 =1–y –3 x0. 1 1 0 1 y –3 =1 ––––––––––––––––––––––––––––––––––––––––––––––––––––– z (3) 0 0 0 1 1 z (3). 0 0 0 1 2z (3) 0 0 1 1 2z (3) 0. 0 0 1 0 –y 0 x2 4 1 0 1 0 y 0 =0–y –4 x0. 0 0 0 0 y –4 =0 ––––––––––––––––––––––––––––––––––––––––––––––––––––– z (4) 0 0 1 1 z (4). 0 0 1 0 s 0 0 1 1s. 0 0 0 0 0 0 1 0 y 0 0 1 0y. 0 1 1 0 =================================================== Example 11.6

19. October 2005Michael Frank, FAMU-FSU College of Engineering 19 C++ function for division of unsigned 32-bit integers unsigned int myDivide // DEFINE FUNCTION myDivide(): (unsigned int dividend, // Argument 0: Number to be divided. unsigned int divisor, // Argument 1: Number to divide it by. unsigned int &remainder) // Argument 2: Place to put remainder. {unsigned int quotient = 0; // Quotient: Initially zero. int position = 0; // Bit position: Initially zero. while (!(divisor & (1<<31))) {// While divisor MSB is empty, position++; // Increment bit position, divisor <<= 1; } // & shift divisor left. do{quotient <<= 1; // Repeatedly, make room for quotient bit; if (dividend >= divisor) { // if we can do a subtraction here, dividend -= divisor; // then do it, quotient |= 1; } // and set quotient bit to 1; divisor >>= 1; } // shift divisor right to a new position; while (--position >= 0); // decrement pos and continue while >=0 remainder = dividend; // Remainder is the remaining dividend. return quotient;} // Return quotient (& remainder).

20. October 2005Michael Frank, FAMU-FSU College of Engineering 20 Equivalent MIPS assembly for 32-bit unsigned division myDivide: move$v0, $zero # quotient := 0; move$t0, $zero # position := 0; leftShift: and$t1, $a1, 0x80000000 # while (divisor & 0x80000000 bne$t1, $zero, doTop # != 0) { addi$t0, $t0, 1 # position++; sll$a1, $a1, 1 # divisor <<= 1; bleftShift # } doTop: sll$v0, $v0, 1 # do { quotient <<= 1; sltu$t1, $a0, $a1 # $t4 := (dividend < divisor) bne$t1, $zero, endIf # if ($t4 == 0) {// d’dend >= d’sor subu$a0, $a0, $a1 # dividend -= divisor; or$v0, $v0, 1 # quotient |= 1; } endIf: srl$a1, $a1, 1 # divisor >>= 1; addi$t0, $t0, -1 # position--; bgez$t0, doTop # } while (position >= 0); endFor: sw$a0, 0($a2) # rem := remainder; jr$ra # return.

21. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 21 Signed Division Method 1 (indirect): strip operand signs, divide, set result signs Dividend Divisor QuotientRemainder z = 5 x = 3  y = 1 s = 2 z = 5 x = –3  y = –1 s = 2 z = –5 x = 3  y = –1 s = –2 z = –5 x = –3  y = 1 s = –2 Method 2 (direct 2’s complement): develop quotient with digits –1 and 1, chosen based on signs, convert to digits 0 and 1 Restoring division: perform trial subtraction, choose 0 for q digit if partial remainder negative Nonrestoring division: if sign of partial remainder is correct, then subtract (choose 1 for q digit) else add (choose –1)

22. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 22 11.5 Hardware Dividers Figure 11.12 Hardware divider based on the shift-subtract algorithm.

23. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 23 The Shift Part of Shift-Subtract Figure 11.13 Shifting incorporated in the connections to the partial remainder register rather than as a separate phase.

24. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 24 High-Radix Dividers Radix-4 division in dot notation. z (j) = 4z (j  1)  (y k  2j+1 y k  2j ) two x 2 k with z (0) = z and z (k/2) = 2 k s | shift | |––––––– subtract –––––––| Assume k even

25. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 25 Array Dividers Figure 11.14 Array divider for 8/4-bit unsigned integers.

26. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 26 11.6 Programmed Division MiniMIPS instructions related to division div $s0,$s1# Lo = quotient, Hi = remainder divu $s2,$s3# unsigned version of division mfhi $t0# set $t0 to (Hi) mflo $t1# set $t1 to (Lo) Compute z mod x, where z (singed) and x > 0 are integers Divide; remainder will be obtained in Hi if remainder is negative, then add |x| to ( Hi ) to obtain z mod x else Hi holds z mod x Example 11.7

27. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 27 Figure 11.15 Register usage for programmed division superimposed on the block diagram for a hardware divider. Division via Repeated Subtractions Example 11.8 (MiniMIPS shift-add program for division)

28. July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 28 Divider vs Multiplier: Hardware Similarities Figure 11.12Figure 11.4 Figure 11.14Figure 11.7 Turn upside-down