Presentation on theme: "Advanced Silicon/Silicon-Germanium Device Simulations John Barker in collaboration with Asen Asenov, Mirela Borici, Scott Roy, Jeremy Watling, Richard."— Presentation transcript:
Advanced Silicon/Silicon-Germanium Device Simulations John Barker in collaboration with Asen Asenov, Mirela Borici, Scott Roy, Jeremy Watling, Richard Wilkins, Lianfeng Yang Nanoelectronics Research Centre Department of Electronics and Electrical Engineering University of Glasgow UK SiGe Research Programme Review Meeting, 3rd April, 2003
Outline Is silicon near its end? Physics, Modelling and Simulation Interface Roughness Silicon-Germanium studies Advanced Simulation methodology Advanced Devices Fully quantum atomistic simulation Summary
1. Is silicon near its end? House of Commons Select Committee (2002) Red brick wall between Fundamental limit: 2015 Theory Limit: nm Suggests: single electronics,magnetic and atomic devices carbon nanotubes, quantum computing and other radical alternatives to CMOS be pursued Concentrate on microprocessor design and architecture 1978:red brick wall 0.25µm limit,alternatives included magnetic bubble logic conv. & quantum devices based on GaAs and InP!
Atomic scale MOSFET in the near future ?? We still firmly believe the Si route is the best
Reality check: Scaling of MOSFETs to decanano dimensions The accelerating road map! House of Lords
MOSFET Technology The accelerating road map! 50 nm gates 30 nm gates Intel Raised Source Drain: power reduction High k dielectric: leakage, avoid too thin SOI : kill leakage; better materials:strained Si, SiGe Paradigm shift
Beyond the House of Lords! Intel 20 nm transistor Intel 10 nm transistor (2002)
The IBM 6 nm silicon transistor (IEDM 2002) demonstrated
Silicon Nanoelectronics Todays transistors 130 nm to 90 nm Tomorrows transistors: still silicon! Projection: a vision down to 4nm-2 nm exists corresponding to a timescale Huge possibilities: versatile platform for new and emerging technologies US, Japan Europe, UK?? (width of a Carbon NT) new programmes
Device issues (partial): routes forward exist Leakage Power dissipation Voltage scaling Frequency Direct S-D tunnelling Off-On control Fluctuation phenomena device architecture engineered Si compatible materials novel dielectrics SOI RSD interface roughness many-body mobility degradation atomistic effects quantum effects
Will need different kinds of transistors in system blocks: Datapaths (speed, leakage) Dedicated DSP (power, leakage) Memory (density is main concern) Analogue Power and leakage determine the size ratios between these blocks Number of different transistors types is determined by parameter spread Less devices could solve the problem, but, need control of the threshold (4th terminal), with strong transfer function. System solutions: adaptive control, coding,... System issues
Future of mainstream electronics Silicon nanoelectronics Device design and System design required together to solve issues of: power, leakage, fluctuations, stability Silicon, strained silicon, silicon-germanium, germanium III-V on silicon/germanium good versatile materials technology ALL subscribed to by major industry players Lifetime: beyond 2025 THIS IS OUR MOTIVATION FOR BEING IN THE SiGe Project
2. Physics, modelling and simulation Why is simulation useful? Part of the design-optimisation cycle Extraction of circuit parameters Calibration and extension of commercial tools Develop device physics and architecture Getting ahead of the game.
Simulation tools Development of a fully bipolar (electrons and holes) 2-D Full-Band Monte Carlo device simulator for Si/strained Si/SiGe that includes degeneracy, high doping effects, advanced screening models, quantum potential and interface roughness scattering. Down to 30 nm. Device Physics and new Simulation tools –Investigation of carrier transport and scattering at interfaces –New non-perturbative models for interface roughness scattering –Effects of degeneracy, high doping, band-gap narrowing –Advanced screening models –Quantum transport extensions: density gradient, quantum potential, Wigner function, Green function –Atomistic studies: classical, semi-classical and full quantum transport Design - optimisation with partners –Layer and device design for consortium partners –Modelling and scaling study of high linearity MODFETs, based on experimental data from Daimler Chrysler Applications to partners and industry SiGe MODFETs, RF devices, Si, strained Si and SiGe well tempered devices, double gate devices, atomistic devices. Course on Device Modelling 2 nd -5 th July 2002 Summary of Progress ( ) - see also posters
An extension of semi-classical Boltzmann-Fuchs theory, that is suitable for efficient inclusion within the Monte Carlo framework. Probability of specular or diffuse scattering is chosen according to the carrier k-vector and incident scattering angle. This overcomes one of the major failings of the traditional semi-classical model. The scattering from a rough surface, has strong randomizing effects, resulting in a broad distribution over the emergent angles, while scattering from a smoother interface has a high probability at emergent angles close to specular 4. Interface Roughness: new non-perturbative model
Gaussian auto-covariance Exponential auto-covariance RMS height: 0.5nm Correlation Length: L c = 3nm Diffuse scattering, depends on the autocorrelation function considered.
Polar plot of probability of scattering through a given angle in surface P=1.0 diffuse specular diffuse
Semi-classical model versus ab-initio quantum calculations
Ab initio interface scattering:Gaussian wavepacket scattering off a smooth interface Initial Motion of Wave Packet TimeReal Spacek (Fourier) Space 0.0 ps 0.02 ps 0.05 ps Electron rest mass, V(r) = 0; k x0 = k y0 = 10 9 m -1 ; E = 76meV
Ab initio interface scattering:Gaussian wavepacket scattering off a rough interface Initial Motion of Wave Packet TimeReal Spacek (Fourier) Space 0.0 ps 0.02 ps 0.05 ps Electron rest mass, V(r) = 0; k x0 = k y0 = 10 9 m -1 ; E = 76meV back scattering & diffuse scattering
4. Silicon-Germanium Studies: 2 examples Simulation of 67nm IBM Relaxed and Strained Si n-MOSFET. Provides test for interface roughness simulations Simulation of 67nm IBM Relaxed and Strained Si n-MOSFET. Provides test for interface roughness simulations Optimizations of Si/SiGe 70 nm MODFET for RF and high linearity applications: using Daimler-Chrysler data Optimizations of Si/SiGe 70 nm MODFET for RF and high linearity applications: using Daimler-Chrysler data (part of support for experimental RF and linear systems programme) (part of support for experimental RF and linear systems programme) Other work: see posters
4.1 Simulation of IBM Relaxed and Strained Si n-MOSFET 4.1 Simulation of 67nm IBM Relaxed and Strained Si n-MOSFET Comparison between the n-type Strained Si and control Si MOSFETs: 67nm effective channel length Similar processing and the same doping conditions For the strained Si MOSFET: 20nm strained Si layer thickness Strained Si on relaxed SiGe (Ge content: 15%) K.Rim, et. al., Symposium on VLSI Technology 2001
I d -V g Current Characteristics: Monte Carlo v Experiment
I d -V g Current Characteristics (higher fields)
Channel Velocities: Monte Carlo Electron Velocities along the channel of IBM 67nm Si n-MOSFET, V d =V g =1V
Strained Si 67nm n-channel MOSFET Structure
I d -V g Current Characteristics for strained Si n-MOSFET
Study 2: Optimizations of Si/SiGe MODFET for RF and high linearity applications Based on the understanding of a Daimler-Chrysler 70nm Si/SiGe MODFET Aim for high RF performance and high linearity: RF : f T =f(g m,C g, etc); f max =f(f T, g m,C gs,C gd, g ds,etc) Linearity : PIP3=4 g m /(g m2 R L ) High is Good Trade-off designs between f T and linearity Gate-to-channel distance Gate position (L gs /L ds ) Doping in the channel (MODFETs vs. DCFETs) Effects of scaling on RF performance and linearity L. Yang, A. Asenov, M. Boriçi, J. R. Watling, J. R. Barker, S. Roy, K. Elgaid1, I. Thayne, T. Hackbarth
Device Structure MODFET DaimlerChrysler structure double-side modulation doping high mobility MODFET with doped channel sandwich-like doped channel reduced mobility high carrier density Doped Channel FET (DCFET) sandwich-like doped channel without modulation doping high carrier density lower mobility
Calibrations of drift-diffusion simulators Calibrated I d -V g characteristics of DaimlerChrysler 70nm Si/SiGe MODFET
One example: Effects of the gate-to-channel distance Effects of the gate-to-channel distance d on the linearity (PIP3); the inset is the effect of d on the transconductance g m small d is worst for linearity but good for RF
Results Trade-off designs for RF performance and linearity Gate-to-channel distance d: decreasing d enhances RF, but lowers linearity Gate position L gs /L ds : increasing L gs /L ds achieves high linearity, but reduces g m and drive current I D Doped channel – leads to good linearity, although gives a decrease for g m and drive current I D Scaling improved RF performance slightly decreased linearity
5. Development of Advanced Simulation Methodologies SiGe heterostructure FET models Full Band Monte Carlo Device & bulk simulation,Poisson-Schrödinger Drift Diffusion, Hydrodynamic, Quantum corrected versions Density gradient & space-dependent mass Wigner equation (2002) Quasi-Classical atomistic simulator(2002) unique to Glasgow Full Non-Equilibrium Green Function simulator (2003) Green function - T-matrix quantum hydrodynamic atomistic simulator (2003) unique to Glasgow Grants NASA IBM EPSRC (Platform) Ind. partners NEW
Possible quantum effects within a MOSFET Gate Tunnelling B-to-B Tunnelling S-to-D Tunnelling Quantum Confinement Quantum transport
6. Advanced Devices Intel have announced conventional MOSFETs scaled down to 10nm, and IBM have even announced a 6nm channel length. The scaling of this design below 10nm is likely to require intolerably thin gate oxides and unacceptably high channel doping, therefore advocating a departure from the conventional MOSFET concept. One of the most promising new device structures is the double-gate MOSFET, with the possibility of scaling to 10nm and below, where direct source-drain tunnelling will become a real possibility. 4 nm Double gate MOSFET: An Artists Impression
ClassicalQuantum 6.1 Double-Gate MOSFET structure Based on structure of Z. Ren, R. Venugopal, S. Datta, M. Lundstrom, D. Jovanovic, J. Fossum IEDM Technical Digest pp (2000) density-gradient
Source-Drain Tunnelling Classical and Density Gradient Simulations I D -V G characteristics obtained from classical and calibrated DG simulations for double gate MOSFETs with channel lengths of 20nm and 4nm. V D =1V, V G is applied to both gates. The quantum mechanical threshold voltage shift, V T, is illustrated.
Non-equilibrium Greens Function Method Equations of motion for Greens functions: (E-H- r ) G r (r,r',E) = (r-r') (E-H- r ) G < (r,r',E) = < G a (r,r',E) >(E-H- r ) G > (r,r',E) = > G a (r,r',E) r represents self-energy due to open boundaries and scattering r = U g r (surface) U Poissons equation
Striations in DOS plots are sub-bands. Spectral shift evident near source barrier. Multiple sub-bands are required for accurate scattering calculations MOSFET Quantum Mechanical Effects: Sub-bands Jovanovich et al (2001) Quantum mechanical DOS (spectral function) data taken at Si-SiO2 interface
Non-equilibrium Greens Function and low-cost Density Gradient Simulations for double gate structure I D -V G characteristics obtained from Non-equilibrium Greens function and calibrated DG simulations for double gate MOSFETs with gate lengths ranging from 20nm to 4nm. V D =1V.
6.2 The transition to atomistic devices need more advanced simulation tools 4 nm
Atomistic effects: being studied in depth at Glasgow Discrete nature of charge Discrete nature of dopants Line edge roughness Interface roughness Atomic segregation Discrete many-body carrier interactions Fischetti asenov et al
Large systems: self-averaging Small systems: random micro-configurations Conventional perturbation methods inadequate including NEGF Exact non-asymptotic T-matrix partial-wave analysis of hard sphere model for impurities and roughness Results sensitive to configuration No self-averaging Treat impurity/roughness scattering non-perturbatively 7. Fully quantum atomistic simulation Barker, Physica (2003) open 3D slab confined open box geometry
Random impurity potential: the Kohn and Luttinger ansatz Fourier transform structure factor standard GF theory ensemble average
N = 3 N=10 N=100 N=1000 self-averaged strong interference
Impurity array: N short range scatterering centres G= … G T matrix X STANDARD NON-EQUILIBRIUM GREEN FUNCTION FAILS
T-matrix approximation: no self-averaging interference term cross-section~
openslab box ka=0.25 k=0.1 a=2.5 nm low energy ka=1 a=2.5 nm medium energy incoming current interferes with scattered current from impurity & boundary
classical trajectories strong blocking by impurities or remote fluctuation pot
strong diffraction effects; some multiple scattering Box geometry 25 X 25 X 25 nm :density & current meandering flow between impurities & vortices S D S D ka=2.5 Si 300K
Transmission coefficients and conductance Compute conductance using Landauer formula Results for devices with < 25 nm geometries Conductance very sensitive to impurity cluster orientation Conductance not given by standard GF or Boltzmann Flow between vortices is reversible: quasi-ballistic suggests flow between impurities and vortices is relaxive Conjecture: Thermal superposition: Lundstrom picture Why do small devices work? actual flow is semi-classical fluid but within a renormalised fluctuation potential landscape.
8. Summary A new interface roughness scattering model developed:gives good agreement with 67 nm n-channel Si and Strained Si MOSFETs. Design and scaling studies provide useful results for RF and linear devices A state-of-the-art Monte Carlo simulator Practical and new ab initio quantum simulation tools Role of atomicity and fluctuations Advanced device studies down to 4 nm scale Silicon nanoelectronics has a great future -lets not ignore it!