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**Advanced Silicon/Silicon-Germanium**

UK SiGe Research Programme Review Meeting, 3rd April, 2003 Advanced Silicon/Silicon-Germanium Device Simulations John Barker in collaboration with Asen Asenov, Mirela Borici, Scott Roy, Jeremy Watling, Richard Wilkins, Lianfeng Yang Nanoelectronics Research Centre Department of Electronics and Electrical Engineering University of Glasgow

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Outline Is silicon near its end? Physics, Modelling and Simulation Interface Roughness Silicon-Germanium studies Advanced Simulation methodology Advanced Devices Fully quantum atomistic simulation Summary

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1. Is silicon near its end? House of Commons Select Committee (2002) Red brick wall between Fundamental limit: 2015 Theory Limit: nm Suggests: single electronics,magnetic and atomic devices carbon nanotubes, quantum computing and other radical alternatives to CMOS be pursued Concentrate on microprocessor design and architecture 1978:red brick wall 0.25µm limit,alternatives included magnetic bubble logic conv. & quantum devices based on GaAs and InP!

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**Atomic scale MOSFET in the near future ??**

We still firmly believe the Si route is the best

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**Reality check: Scaling of MOSFETs to decanano dimensions**

House of Lords The accelerating road map!

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**The accelerating road map!**

Paradigm shift MOSFET Technology Intel 50 nm gates nm gates Raised Source Drain: power reduction High k dielectric: leakage, avoid too thin SOI : kill leakage; better materials:strained Si, SiGe

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**Beyond the House of Lords!**

2001-2 Intel 20 nm transistor Intel 10 nm transistor (2002)

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**The IBM 6 nm silicon transistor (IEDM 2002)**

demonstrated

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**Silicon Nanoelectronics**

Today’s transistors 130 nm to 90 nm Tomorrows transistors: still silicon! Projection: a vision down to 4nm-2 nm exists corresponding to a timescale Huge possibilities: versatile platform for new and emerging technologies new programmes US, Japan Europe, UK?? (width of a Carbon NT)

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**Device issues (partial): routes forward exist**

Leakage Power dissipation Voltage scaling Frequency Direct S-D tunnelling Off-On control Fluctuation phenomena device architecture engineered Si compatible materials novel dielectrics SOI RSD interface roughness many-body “mobility” degradation atomistic effects quantum effects

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System issues Will need different kinds of transistors in system blocks: Datapaths (speed, leakage) Dedicated DSP (power, leakage) Memory (density is main concern) Analogue Power and leakage determine the size ratios between these blocks Number of different transistors types is determined by parameter spread Less devices could solve the problem, but, need control of the threshold (4th terminal), with strong transfer function. System solutions: adaptive control, coding, ...

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**Future of mainstream electronics**

Silicon nanoelectronics Device design and System design required together to solve issues of: power, leakage, fluctuations, stability Silicon, strained silicon, silicon-germanium, germanium III-V on silicon/germanium good versatile materials technology ALL subscribed to by major industry players Lifetime: beyond 2025 THIS IS OUR MOTIVATION FOR BEING IN THE SiGe Project

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**2. Physics, modelling and simulation**

Why is simulation useful? Part of the design-optimisation cycle Extraction of circuit parameters Calibration and extension of commercial tools Develop device physics and architecture Getting ahead of the game.

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**Summary of Progress (2002-2003) - see also posters**

Simulation tools Development of a fully bipolar (electrons and holes) 2-D Full-Band Monte Carlo device simulator for Si/strained Si/SiGe that includes degeneracy, high doping effects, advanced screening models, quantum potential and interface roughness scattering. Down to 30 nm. Device Physics and new Simulation tools Investigation of carrier transport and scattering at interfaces New non-perturbative models for interface roughness scattering Effects of degeneracy, high doping, band-gap narrowing Advanced screening models Quantum transport extensions: density gradient, quantum potential, Wigner function, Green function Atomistic studies: classical , semi-classical and full quantum transport Design - optimisation with partners Layer and device design for consortium partners Modelling and scaling study of high linearity MODFETs, based on experimental data from Daimler Chrysler Applications to partners and industry SiGe MODFETs, RF devices, Si, strained Si and SiGe well tempered devices, double gate devices, atomistic devices. Course on Device Modelling 2nd-5th July 2002

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**4. Interface Roughness: new non-perturbative model**

An extension of semi-classical Boltzmann-Fuchs theory, that is suitable for efficient inclusion within the Monte Carlo framework. Probability of specular or diffuse scattering is chosen according to the carrier k-vector and incident scattering angle. This overcomes one of the major failings of the traditional semi-classical model. The scattering from a rough surface, has strong randomizing effects, resulting in a broad distribution over the emergent angles, while scattering from a smoother interface has a high probability at emergent angles close to specular

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**Gaussian auto-covariance Exponential auto-covariance**

Diffuse scattering, depends on the autocorrelation function considered. Gaussian auto-covariance Exponential auto-covariance RMS height: 0.5nm Correlation Length: Lc = 3nm

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**Polar plot of probability of scattering through a given angle**

surface in diffuse specular P=1.0

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**Semi-classical model versus ab-initio quantum calculations**

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**Ab initio interface scattering:Gaussian wavepacket scattering **

off a smooth interface Time Real Space k (Fourier) Space 0.0 ps 0.02 ps 0.05 ps Initial Motion of Wave Packet Electron rest mass, V(r) = 0; kx0 = ky0 = 109 m-1; E = 76meV

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**Ab initio interface scattering:Gaussian wavepacket **

scattering off a rough interface Time Real Space k (Fourier) Space 0.0 ps 0.02 ps 0.05 ps Initial Motion of Wave Packet back scattering & diffuse Electron rest mass, V(r) = 0; kx0 = ky0 = 109 m-1; E = 76meV

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**4. Silicon-Germanium Studies: 2 examples**

Simulation of 67nm IBM Relaxed and Strained Si n-MOSFET. Provides test for interface roughness simulations Optimizations of Si/SiGe 70 nm MODFET for RF and high linearity applications: using Daimler-Chrysler data (part of support for experimental RF and linear systems programme) Other work: see posters

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**4.1 Simulation of 67nm IBM Relaxed and Strained Si n-MOSFET**

Comparison between the n-type Strained Si and control Si MOSFETs: 67nm effective channel length Similar processing and the same doping conditions For the strained Si MOSFET: 20nm strained Si layer thickness Strained Si on relaxed SiGe (Ge content: 15%) K.Rim, et. al., Symposium on VLSI Technology 2001

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**Id-Vg Current Characteristics: Monte Carlo v Experiment**

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**Id-Vg Current Characteristics**

(higher fields)

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**Channel Velocities: Monte Carlo**

Electron Velocities along the channel of IBM 67nm Si n-MOSFET, Vd=Vg=1V

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**Strained Si 67nm n-channel MOSFET Structure**

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**Id-Vg Current Characteristics for strained Si n-MOSFET**

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**Study 2: Optimizations of Si/SiGe MODFET for RF and high linearity applications**

Based on the understanding of a Daimler-Chrysler 70nm Si/SiGe MODFET Aim for high RF performance and high linearity: RF: fT=f(gm,Cg, etc); fmax=f(fT, gm,Cgs,Cgd, gds,etc) Linearity: PIP3=4gm/(gm2 RL) High is Good Trade-off designs between fT and linearity Gate-to-channel distance Gate position (Lgs/Lds) Doping in the channel (MODFETs vs. DCFETs) Effects of scaling on RF performance and linearity L. Yang, A. Asenov, M. Boriçi, J. R. Watling, J. R. Barker, S. Roy, K. Elgaid1, I. Thayne, T. Hackbarth

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**Device Structure MODFET DaimlerChrysler structure**

double-side modulation doping high mobility MODFET with doped channel sandwich-like doped channel reduced mobility high carrier density Doped Channel FET (DCFET) without modulation doping lower mobility

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**Calibrations of drift-diffusion simulators**

Calibrated Id-Vg characteristics of DaimlerChrysler 70nm Si/SiGe MODFET

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**One example: Effects of the gate-to-channel distance**

small d is worst for linearity but good for RF Effects of the gate-to-channel distance d on the linearity (PIP3); the inset is the effect of d on the transconductance gm

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Results Trade-off designs for RF performance and linearity Gate-to-channel distance d: decreasing d enhances RF, but lowers linearity Gate position Lgs/Lds: increasing Lgs/Lds achieves high linearity, but reduces gm and drive current ID Doped channel – leads to good linearity, although gives a decrease for gm and drive current ID Scaling improved RF performance slightly decreased linearity

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**5. Development of Advanced Simulation Methodologies**

SiGe heterostructure FET models Full Band Monte Carlo Device & bulk simulation,Poisson-Schrödinger Drift Diffusion, Hydrodynamic, Quantum corrected versions Density gradient & space-dependent mass Wigner equation (2002) Quasi-Classical atomistic simulator(2002) unique to Glasgow Full Non-Equilibrium Green Function simulator (2003) Green function - T-matrix quantum hydrodynamic atomistic simulator (2003) unique to Glasgow Grants NASA IBM EPSRC (Platform) Ind. partners NEW

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**Possible quantum effects within a MOSFET**

Quantum transport Gate Tunnelling B-to-B S-to-D Quantum Confinement

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**An Artist’s Impression**

6. Advanced Devices Intel have announced conventional MOSFETs scaled down to 10nm, and IBM have even announced a 6nm channel length. The scaling of this design below 10nm is likely to require intolerably thin gate oxides and unacceptably high channel doping, therefore advocating a departure from the conventional MOSFET concept. One of the most promising new device structures is the double-gate MOSFET, with the possibility of scaling to 10nm and below, where direct source-drain tunnelling will become a real possibility. 4 nm Double gate MOSFET: An Artist’s Impression

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**6.1 Double-Gate MOSFET structure**

density-gradient Classical Quantum Based on structure of Z. Ren, R. Venugopal, S. Datta, M. Lundstrom, D. Jovanovic, J. Fossum IEDM Technical Digest pp (2000)

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**Source-Drain Tunnelling Classical and Density Gradient Simulations**

ID-VG characteristics obtained from classical and calibrated DG simulations for double gate MOSFETs with channel lengths of 20nm and 4nm. VD=1V, VG is applied to both gates. The quantum mechanical threshold voltage shift,VT, is illustrated.

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**Non-equilibrium Green’s Function Method**

Equations of motion for Green’s functions: (E-H-Sr) Gr (r,r',E) = d(r-r') (E-H-Sr) G< (r,r',E) = S< Ga (r,r',E) (E-H-Sr) G> (r,r',E) = S> Ga (r,r',E) Sr represents self-energy due to open boundaries and scattering Sr = U gr (surface) U Poisson’s equation (r,r’) are indices for the matrix equation These equations are solved only inside the green box. Yet Sch Eqn or the above equations are not being solved for a closed system. The open boundaries in the contacts are included via a self-energy.

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**MOSFET Quantum Mechanical Effects: Sub-bands**

Jovanovich et al (2001) Quantum mechanical DOS (spectral function) data taken at Si-SiO2 interface Striations in DOS plots are sub-bands. Spectral shift evident near source barrier. Multiple sub-bands are required for accurate scattering calculations

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**Non-equilibrium Green’s Function and low-cost Density Gradient Simulations for double gate structure**

ID-VG characteristics obtained from Non-equilibrium Green’s function and calibrated DG simulations for double gate MOSFETs with gate lengths ranging from 20nm to 4nm. VD=1V.

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**6.2 The transition to atomistic devices**

need more advanced simulation tools 4 nm

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**Atomistic effects: being studied in depth at Glasgow**

Discrete nature of charge Discrete nature of dopants Line edge roughness Interface roughness Atomic segregation Discrete many-body carrier interactions Fischetti asenov et al

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**7. Fully quantum atomistic simulation**

Barker, Physica (2003) Large systems: self-averaging Small systems: random micro-configurations Conventional perturbation methods inadequate including NEGF Exact non-asymptotic T-matrix partial-wave analysis of hard sphere model for impurities and roughness open 3D slab confined open box geometry Results sensitive to configuration No self-averaging Treat impurity/roughness scattering non-perturbatively

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**Random impurity potential: the Kohn and Luttinger ansatz**

Fourier transform structure factor ensemble average standard GF theory

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N = N= N= N=1000 self-averaged strong interference

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**X Impurity array: N short range scatterering centres T matrix G= + +**

… X G≠ STANDARD NON-EQUILIBRIUM GREEN FUNCTION FAILS

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**T-matrix approximation: no self-averaging**

interference term cross-section~

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open slab box ka=0.25 k=0.1 a=2.5 nm low energy ka=1 a=2.5 nm medium energy incoming current interferes with scattered current from impurity & boundary

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**classical trajectories**

strong blocking by impurities or remote fluctuation pot

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**3 impurity system: box geometry z=0 plane**

quantum flow meanders through despite classical blocking

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**Box geometry 25 X 25 X 25 nm :density & current**

ka=2.5 Si 300K S D S D strong diffraction effects; some multiple scattering meandering flow between impurities & vortices

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**Transmission coefficients and conductance**

Why do small devices work? Compute conductance using Landauer formula Thermal superposition: Lundstrom picture Results for devices with < 25 nm geometries Conductance very sensitive to impurity cluster orientation Conductance not given by standard GF or Boltzmann Flow between vortices is reversible: quasi-ballistic suggests flow between impurities and vortices is relaxive Conjecture: actual flow is semi-classical fluid but within a renormalised fluctuation potential landscape.

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8. Summary A new interface roughness scattering model developed:gives good agreement with 67 nm n-channel Si and Strained Si MOSFETs. Design and scaling studies provide useful results for RF and linear devices A state-of-the-art Monte Carlo simulator Practical and new ab initio quantum simulation tools Role of atomicity and fluctuations Advanced device studies down to 4 nm scale Silicon nanoelectronics has a great future -lets not ignore it!

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