1. Metallization: Contact to devices, interconnections between devices and to external Signal (V or I) intensity and speed (frequency response, delay)

2. Issues in VLSI Metallization  Speed: switching speed, RC delay  Intensity: electromigration ( I ), electric breakdown ( V )  Stability: contact interface, stable I-V characteristics  Voltage drop: IR drop reduces voltage on transistor  Area: connection wires have to be narrow as device density increases

3. Multi-level Metallization Lower levels: fine connections to individual devices Upper levels: thicker/wider common connections

4. Multi-level metal connections

5. Pit Formation of Al Contact with Si High solubility of Si in Al (~1%) Al spikes

6. Silicide Contacts

7. Phase Diagram and Formation Sequence of Silicide

8. Salicide (Self-aligned silicide layer) N-channel MOS with poly Si gate Ti deposition and annealing, TiSi 2 formation at source, drain and gate Etch away unreacted Ti Apply dielectrics and final metallization with Al

9. Multi-level Metallization

10. Plug Filling

11. Chemical Mechanical Polishing (CMP)

12. Damascene processes Dual damascene Metal plugs in planar SiO 2 Interlayer dielectric deposit Trench patterning & RIE for metal lines Metal deposition CMP Single barrier layer and metal deposition steps, same metal for plugs and lines

13. Electromigration Effects Void Pile-up Electron wind and field-driven atomic migration Bamboo-structured wire Electromigration-resistant

14. Triple diffusion 2-sided diffusion Double-diffused epitaxial p-well (tub) n-well Epitaxy double-well Device Isolation

15. CMOS Technology CMOS inverter Simple CMOS layout

16. Twin-well CMOS process

17. Lateral Isolation Localized oxidation isolation (LOCOS) Trench isolation Oxidation isolation

18. Simple MOS process (a) Source & drain p + diffusion (b) Wet oxidation for field oxide (c) Dry oxidation for gate oxide (d) Al metallization for gate and contacts to S & D

19. Poly-Si gate NMOS process Field oxide growth and opening etching Gate oxide growth and poly-Si deposit Gate, source & drain n + diffusion PSG CVD, lithography and metallization

20. General Process Integration Considerations for ULSI  In mask and process designs, tolerances for variations in line width, junction depth and width, depletion zone width, film thickness, mask-making and alignment  Use self-aligned process if possible: e.g. source & drain implantation, salicide process  Step heights (vertical profile variation) must ensure a positive focus margin (FM)  Large process window and small sensitivity: tolerate variation in equipment performance  On-line monitoring of control parameters

21. Wafer with IC Chips Thin film pads for wire bonding Bonding & Packaging

22. Plastic-encapsulated package Back side of IC chip bond to a metallized ceramic substrate Au wires connecting the IC and pins

23. Wire bonding process

24. Flip-chip bonding with Pb-Sn solder ball in contact with a ceramic substrate More interconnect pad (>100) allowed Shorter connection length, less coupling