1. Presenter : Ching-Hua Huang 2013/9/16 Visibility Enhancement for Silicon Debug Cited count : 62 Yu-Chin Hsu; Furshing Tsai; Wells Jong; Ying-Tsai Chang Novas Software, San Jose, CA Design Automation Conference (DAC), 2006 43rd ACM/IEEE National Sun Yat-sen University Embedded System Laboratory

2. Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require the instrumentation of on-chip logic for extracting the internal register data from in situ silicon. Unfortunately, lack of visibility of the combinational network values impedes the ability to functionally debug the silicon part. Visibility enhancement techniques enable the virtual observation of combinational nodes with minimal computational overhead. These techniques also cover the register selection analysis for DFD and multi-level design abstraction correlation for viewing values at the register transfer level (RTL). 2

3. Experimental results show that visibility enhancement techniques can leverage a small amount of extracted data to provide a high amount of computed combinational signal data. Visibility enhancement provides the needed connection between data obtained from the DFD logic and HDL simulation-related debug systems. 3

4. 4 Introduction  The process of IC designs can be broken into two stages  Key factors which make silicon debug difficult include: ◦ Limited silicon signal data visibility ◦ Silicon errors may either be functional bugs or physical defects ◦ Silicon debug data is usually associated with a gate-level netlist |--------First stage------| |----Second stage---| DecreasingIncreasing

5. 5  Manufacturing Test ◦ To check the physical defects ◦ Based on DFT and ATPG  System Validation ◦ To ensure the silicon operates according to specification ◦ Based on DFD logic  Many DFD implementations leverage DFT circuitry.  DFD is the access mechanism that provides in-situ scan register visibility ◦ Data to Debug Flow Scan control Combinational logic DFTDFT DFD Real-time clock & reset control

6. 6  Finding and analyzing the problems in silicon is dreadfully tedious and time consuming. ◦ DFD provide very limited signal access and visibility into a device. ◦ DFT allows observation of states in scan chain, but it is still limited by only the register signals.  The data extracted from device is usually mapped to gate-level netlist. ◦ Designers normally implement the design at the behavioral- level.  This paper propose a methodology to resolve the above issues.

7. 7 [1] [2] User Wants and Needs [1] [2] User Wants and Needs The time required to move from prototype to volume production is increasing This paper: Visibility Enhancement for Silicon Debug This paper: Visibility Enhancement for Silicon Debug [5] DFT and ATPG [5] DFT and ATPG A common methodology utilized in approximately 82% of designs [8] DFD [8] DFD [4][16] More sophisticated DFD methodologies [4][16] More sophisticated DFD methodologies [17] A Reconfigurable Design-for-Debug Infrastructure [17] A Reconfigurable Design-for-Debug Infrastructure Add internal monitoring and breakpoints Extract values to be observed during run real-time observation Around five percent of all designs contain some type of DFD Proposed method

8. 8  This methodology includes three main steps: ◦ Essential Signal Analysis:  Analyze design (RTL, gate) and provide optimal (minimal and sufficient) set of signals to be observed ◦ Data expansion:  Using the knowledge of the design function to computes the missing data. ◦ Gate-to-RTL Correlation:  Map the gate level signals back to RTL

9. 9  ESA starts by inferring the HDL description ◦ It recursively traverses inferred logic netlist, analyzes the logic equations for each functional block.  The ESA technology can also be applied in regression simulation. ◦ For regression simulation  1.ESA analyzes the RTL or netlist code to find the storage elements, memory elements, and the primary inputs.  2.Only dumping the essential signals  3.Full visibility can be achieved using the data expansion technology ◦ The regression simulation methodology can reduce the total simulation times for debug.

10. 10  To obtain the maximal visibility of a device. ◦ The quality of essential signal analysis is closely related to the capability of data expansion.  Translate Data for the HDL Domain ◦ The captured data must be translate to properly format for debugging tools ◦ There are a number of steps to this process:  Temporal transformation  Correlate time or cycle to the captured data from silicon world to virtual world  Signal mapping  The data must be associated with the signal names in the HDL design  Format transformation  The data is made available in standard VCD format or Novas FSDB format

11. 11  Expand Captured Data ◦ Computes the missing data by using the knowledge of the design function.  There are two primary differences with the simulation ◦ Data expansion where only the needed value will be computed is a must for users. ◦ The time-processing is not necessary. Data expansion 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 1 0 0 0 1 0 01 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 Cycle NCycle N+1 Cycle N Cycle N+1

12. 12  In general, Silicon signal data is usually easy to assign to gate-level signals  Gate-level netlist and values are difficult for RTL designers to understand and debug ◦ One-to-one correspondence is not always the case after synthesis transformations CorrelationCorrelation 0100101110010110 1101011000110110 1000011111000000 CorrelationCorrelation Gate-level RTL Silicon extracted easy difficult

13. 13  Essential Signal Analysis ◦ How many Percentage of signals can reach the full visibilty ? ◦ As described in ESA, the regression simulation can reduce the total simulation times ?  Gate-to-RTL Correlation ◦ If synthesized an RTL design into gates both with and without preserving hierarchy. ◦ Is this difference will effect our debug ?

14. 14 Working scope # of signals # of essential signals % of signals Case 1138842131909.5% Case 2680880199224814.6% Case 345680741735443.8% Case 1Case 2 Simulation time FSDB file size Simulation time FSDB file size Full dump506 sec.290 MB6 hr. 39 min.2.1 GB No dump132 sec.N/A2 hr. 12 min.N/A ES dump174 sec.25 MB2 hr. 29 min.61.7 MB  Effectiveness of essential signal analysis technology  The regression simulation can reduce the total simulation

15. 15 Gate to RTL correlation  Effectiveness of the gate to RTL correlation technology CountPercentage Total990 Can be mapped20721% 1 statement68469% 2-3 statements545.4% More than 3 statements212.1% Other (floating, scan chain …)242.5% CountPercentage Total952 Can be mapped18019% 1 statement30732% 2-3 statements19420% More than 3 statements21322% Other (floating, scan chain …)586% With preserving hierarchy Without preserving hierarchy It is useful for silicon debug. It will make the silicon debug difficultly.

16. 16  Conclusions ◦ These technologies provide the ability to  Analyze the essential signals  Expand the captured data  Correlation to present gate-level data at the RTL ◦ This experiments show  T he proposed technology is effective  It greatly enhance the comprehension of silicon prototype operation  My comments ◦ This paper was cited from many papers which proposed the approaches of silicon debug. ◦ It discuss about the Gate-to-RTL Correlation  Some issues are similar with my work.