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Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.

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Presentation on theme: "Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic."— Presentation transcript:

1 Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic design process –Understand CAD needs of logic design Reading –Gate-Level Simulation by D’Abreu –Types of Simulators by Trimberger

2 Logic Design Schematic Capture Logic Simulation Logic Synthesis Technology Mapping RTL Description Boolean Logic Equations Cell Library Function Performance Cell Netlist Component Library Redesign Stimulus Redesign Back- Annotation Physical Design Logic Verification

3 Schematic Capture Interactive creation of schematic –schematic - graphical representation of component netlist –netlist - list of components and nets that connect them Schematic editor –component icons »components from library –wiring cleanup –netlist generation »input to synthesis and simulation tools nand2 1 2 3 nand2 1 3 4 nand2 2 3 5 nand2 4 5 6 A B C Netlist Schematic

4 Schematic Capture Requirements Good user interface - like drawing editor Components and icons from library –not just designing from fixed gate primitives Netlist-to-schematic conversion –from synthesis –difficult - like place and route of chips Back-annotation of parasitics and delays Electrical rule checking –cannot connect two outputs together –no floating inputs –fan-in, fan-out restrictions Netlist generation –in standard formats

5 Logic Simulation Simulate behavior of logic design –netlist from schematic capture or synthesis –use behavior of components »from component library »components - gates, registers, memory Goals –functional correctness »validate with lots of test vectors (input stimuli) –timing »runs fast enough on vectors »no hazards or races –manufacturability »functions at speed under delay variations –test generation »simulate faulty circuits

6 Logic Simulation Requirements Accurate –component behavior – component timing Handle large circuits –millions of gates Really fast –millions of simulations for test generation »#1 use of logic simulation –millions of clock cycles »microprocessor booting OS –sometimes with hardware accelerators »e.g. Zycad, Quickturn

7 Logic Synthesis Map from logic equations and FSM to gates –combinatorial and sequential circuits handled separately Goals –speed –power –area –etc. Constraints –target technology –CPU time a’bc + abc + dbc + d b c d b c d

8 Logic Synthesis Requirements Synthesis and optimization –generate gate netlist –optimize it based on constraints Handle large problem sizes –tens of thousands of gates Handle multiple constraints –e.g. minimize area and delay Incorporate technology knowledge –e.g. do not have 1000-input NAND gates No user intervention - press the button Reasonably fast –for an NP-complete problem

9 Technology Mapping Map optimized gates into cell library –FPGA cells –standard cells –PALs Goal –minimize chip/cell area –minimize delay –minimize power consumption Mapper requirements –reasonably fast - NP-complete –handle large libraries –handle large circuits –specialized to technology Cell AOI33 - area 3248 - delay 0.8 - power 0.08

10 Logic Verification Verify that logic matches specification –detect hand design and logic synthesis errors Goal –ensure functional correctness –boolean equations vs. netlist –pinpoint errors Requirements –reasonably fast - NP-complete –handle large circuits –batch and incremental =?

11 Conclusions Competitive logic design is difficult –most problems are NP-hard –heuristics must trade CPU time vs. optimality –algorithms are hard to think about –tools are hard to build Optimal design is technology-specific –different algorithms for different technologies Verification is needed as a cross-check –difficult algorithms => errors in implementation –limited CPU-time => incomplete design process »the Pentium FDIV bug

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