1. Physical Limits of Computing Dr. Mike Frank CIS 6930, Sec. #3753X Spring 2002 Lecture #27 Reversible Computing Theory I: Reversible Logic Models Wed., Mar. 20

2. Administrivia & Overview Don’t forget to keep up with homework!Don’t forget to keep up with homework! –We are  9 out of 14 weeks into the course. You should have earned  ~64 points by now.You should have earned  ~64 points by now. Course outline:Course outline: –Part I&II, Background, Fundamental Limits - done –Part III, Future of Semiconductor Technology - done –Part IV, Potential Future Computing Technologies - done –Part V, Classical Reversible Computing Adiabatic electronics & CMOS logic families, -last week M&WAdiabatic electronics & CMOS logic families, -last week M&W Limits of adiabatics: Friction,Leakage,Power supplies. Fri.,Mon. RevComp theory I: Reversible Logic Models, RevComp theory II: Emulating Irreversible Machines - TODAYLimits of adiabatics: Friction,Leakage,Power supplies. Fri.,Mon. RevComp theory I: Reversible Logic Models, RevComp theory II: Emulating Irreversible Machines - TODAY RevComp theory II: Bounds on Space-Time Overheads - Fri. 3/22RevComp theory II: Bounds on Space-Time Overheads - Fri. 3/22 Physics-based models of computing - Mon. 3/25Physics-based models of computing - Mon. 3/25 (plus ~6 more lectures…)(plus ~6 more lectures…) –Part VI, Quantum Computing –Part VII, Cosmological Limits, Wrap-Up

3. Limits of Adiabatics: Summary Some final remarks.

4. Summary of Limiting Factors When considering adiabaticizing a system: What fraction of system power is in logic? f LWhat fraction of system power is in logic? f L –Vs. Displays, transmitters, propulsion. What fraction of logic is done adiabatically? f aWhat fraction of logic is done adiabatically? f a –Can be all, but w. cost-efficiency overheads. How large is the I on /I off ratio of switches?How large is the I on /I off ratio of switches? –Affects leakage & minimum adiabatic energy. What is the Q sup of the resonant power supply?What is the Q sup of the resonant power supply? What is the relative cost of energy / logic? r $What is the relative cost of energy / logic? r $ –E.g. decreasing power cost by r $ by increasing HW cost by  r $ will not help. “Power premium”

5. Min. energy & R off /R on ratio Note that: c E = C 2 V 2 R on and if dominant leakage is source/drain: P leak = V 2 /R offNote that: c E = C 2 V 2 R on and if dominant leakage is source/drain: P leak = V 2 /R off So: c E P leak = C 2 V 4 /(R off /R on ) E min = 2(c E P leak ) 1/2 = 2CV 2 (R off /R on )  1/2So: c E P leak = C 2 V 4 /(R off /R on ) E min = 2(c E P leak ) 1/2 = 2CV 2 (R off /R on )  1/2 So: Q max = ½CV 2 / (2CV 2 (R off /R on )  1/2 ) = ¼(R off /R on ) 1/2 = ¼(I on /I off ) 1/2So: Q max = ½CV 2 / (2CV 2 (R off /R on )  1/2 ) = ¼(R off /R on ) 1/2 = ¼(I on /I off ) 1/2

6. Minimizing cost/performance $ P = Cost of power in original system$ P = Cost of power in original system $ H = Cost of logic HW in original system$ H = Cost of logic HW in original system $ P = r $ $ H ; $ H = $ P /r $$ P = r $ $ H ; $ H = $ P /r $ For cost-efficiency inverse to energy savings:For cost-efficiency inverse to energy savings: $ tot,min = $ P r $ -1/2 + $ H r $ 1/2 = 2 $ P r $ -1/2$ tot,min = $ P r $ -1/2 + $ H r $ 1/2 = 2 $ P r $ -1/2 $ tot,orig = $ P + $ H = (1+r $ )$ H = ((1+r $ )/r $ ) $ P$ tot,orig = $ P + $ H = (1+r $ )$ H = ((1+r $ )/r $ ) $ P $ tot,orig /$ tot,min = ½(1+r $ )r $ -1/2  ½r $ 1/2 for large r $$ tot,orig /$ tot,min = ½(1+r $ )r $ -1/2  ½r $ 1/2 for large r $

7. Summary of adiabatic limits Cost-effective adiabatic energy savings factor:Cost-effective adiabatic energy savings factor: S a = E conv / E adia in cost-effective adiabatic system Some rough upper bounds on S a : S a  ~ 1/(1  f L ) S a  ~ 1/(1  f a ) S a  ~ ¼(I on /I off ) 1/2 S a  Q sup S a  ~ r $ 1/2 (worse for non-ideal apps)Some rough upper bounds on S a : S a  ~ 1/(1  f L ) S a  ~ 1/(1  f a ) S a  ~ ¼(I on /I off ) 1/2 S a  Q sup S a  ~ r $ 1/2 (worse for non-ideal apps) But, this ignores benefits from adiabatics of denser packing & smaller communications delays in parallel algorithms. (More later.)But, this ignores benefits from adiabatics of denser packing & smaller communications delays in parallel algorithms. (More later.)

8. Reversible Computing Theory I: Reversible Logic Models

9. Reversible Logic Models It is useful to have a logic-level (Boolean) model of adiabatic circuits.It is useful to have a logic-level (Boolean) model of adiabatic circuits. Can model all logic using pipelinable logic elements that consume their inputs.Can model all logic using pipelinable logic elements that consume their inputs. –Warning: In such models Memory requires recirculation! This is not necessarily more energy- efficient in practice for all problems than retractile (non-input consuming) approaches! There is a need for more flexible logic models.There is a need for more flexible logic models. If inputs are consumed, then input  output logic function must be invertible.If inputs are consumed, then input  output logic function must be invertible.

10. Input-consuming inverter: Before:After: inoutinout 0--1 1--0 E.g. SCRL implementation: in out Input arrow indicates input data is consumed by element. Invertible! Alternate symbol: inout

11. Input-consuming NAND gate: Before:After: A BoutA Bout 0 0-- - 1 0 1- 1 0-- - 0 1 1-Input-consuming NAND gate: Before:After: A BoutA Bout 0 0-- - 1 0 1- 1 0-- - 0 1 1- Because it’s irreversible, it has no implementation in SCRL (or any fully adiabatic style) as a stand-alone, pipelined logic element!Because it’s irreversible, it has no implementation in SCRL (or any fully adiabatic style) as a stand-alone, pipelined logic element! An Irreversible Consuming Gate A B out 4 possible inputs, 2 possible outputs. At least 2 of the 4 possible input cases must lead to dissipation!

12. NAND w. 1 input copied? Still not invertible:BeforeAfter A B A’ out A B A’ out 0 0 - - - - 0 1 0 1 - - - - 1 1 1 0 - - - - 1 0 1 1 - -Still not invertible:BeforeAfter A B A’ out A B A’ out 0 0 - - - - 0 1 0 1 - - - - 1 1 1 0 - - - - 1 0 1 1 - - At least 1 of the 2 transitions to the A’=0, out=1 final state must involve energy dissipation of order k B T. How much, exactly? See exercise.At least 1 of the 2 transitions to the A’=0, out=1 final state must involve energy dissipation of order k B T. How much, exactly? See exercise. A B out A’A’ Delay buffer

13. NAND w. 2 inputs copied? Finally, invertible! Before: After: A B A’ B’ out A B A’ B’ out 0 0 - - - - - 0 0 1 0 1 - - - - - 0 1 1 1 0 - - - - - 1 0 1 1 1 - - - - - 1 1 0Finally, invertible! Before: After: A B A’ B’ out A B A’ B’ out 0 0 - - - - - 0 0 1 0 1 - - - - - 0 1 1 1 0 - - - - - 1 0 1 1 1 - - - - - 1 1 0 Any Boolean function can be made invertible by simply preserving copies of inputs in outputs.Any Boolean function can be made invertible by simply preserving copies of inputs in outputs. –Note: Not all output combinations here are legal! Note there are more outputs than inputs.Note there are more outputs than inputs. –We call this an expanding operation. –But, copied inputs can be shared by many gates. A B out A’A’ B’B’

14. SCRL Pipelined NAND A B A B out = AB Inverters only needed to restore A, B --- Can be shared with other gates that take A, B as inputs. 5T Including inverters: 23 transistors Not including inverters: 7 transistors

15. Non-Expanding Gates Controlled-NOT (CNOT) or input-consuming XOR: A B A’ C 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0Controlled-NOT (CNOT) or input-consuming XOR: A B A’ C 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0 Not universal for classical reversible computing. (Even w. other 1 & 2 output gates.)Not universal for classical reversible computing. (Even w. other 1 & 2 output gates.) However, if we add 1-input, 1-output quantum gates, the resulting gate set is universal!However, if we add 1-input, 1-output quantum gates, the resulting gate set is universal! More on quantum computing in a couple of weeks.More on quantum computing in a couple of weeks. AA’A’ B C = A  B Can implement w. a diadic gate in SCRL AA’A’ B C = A  B

16. Subsumes AND, NAND, XOR, NOT, FAN-OUT, …Subsumes AND, NAND, XOR, NOT, FAN-OUT, … Is its own inverse.Is its own inverse. Universal reversible gate!Universal reversible gate! Toffoli Gate (CCNOT) A B C A’ B’ C’ 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 (XOR) A B C A’=A B’=B C’ = C  AB A B’B C A’ C’

17. Fredkin Gate The first universal reversible logic gate to be discovered. (Ed Fredkin, mid 70’s)The first universal reversible logic gate to be discovered. (Ed Fredkin, mid 70’s) B and C are swapped if A=1, else passed unchanged.B and C are swapped if A=1, else passed unchanged. Conserves 1s and 0s.Conserves 1s and 0s. –Requires no power supply, even if 1 and 0 have different energy levels! A B C A’ B’ C’ 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 A B C A’ B’ C’

18. Reversible Computing Theory II: Emulating Irreversible Machines