1. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – SoC Simulation Strategy ECE 747 Digital Signal Processing Architecture SoC Lecture – SoC Simulation Strategy March 27, 2007 W. Rhett Davis NC State University

2. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 2 Today’s Lecture l Why to use SoC Designer l FIR_cascade_DF example in SoC Designer

3. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 3 Our Goal l Area (cost) l Clock Frequency (constraint on system clock freq.) l Power (battery life/MTTF) l Throughput l Latency Determine the quality of our Accelerator Component in terms of… Knowing these things allow us to determine if there is a market for our design

4. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 4 How will you find the following? l Area l Clock Frequency l Power l Throughput l Latency

5. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 5 ARM1176JZF Characteristics l In a 90nm process, at 1V, optimized for speed » Area: 2.65 mm 2 » Clock Frequency: 620 MHz » Power: 0.45 mW/MHz (source: www.arm.com) l We’ll need to scale these numbers to be compatible with our Design Compiler results

6. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 6 Theoretical vs. Observed Throughput l Our accelerators will have a theoretical maximum throughput when simulated by themselves l When simulating with a complete system, the memory accesses become a bottleneck, leading to a smaller observed throughput » observed average throughput (results per cycle) = total no. of results / total no. of cycles l We need the realistic model of the interconnect and memory in SoC Designer to accurately characterize the observed throughput

7. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 7 Today’s Lecture l Why to use SoC Designer l FIR_cascade_DF example in SoC Designer

8. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 8 Similarity to SystemC Flow l Like the SystemC Simulation Flow, this flow will » Use the files Data.txt for input values and Coeffs.txt to configure the filter » Output to the file Output.txt with filtered values » Use a standard SystemC module communicating through sc_signal and sc_fifo channels. l Unlike the SystemC flow… » Test-bench will be discarded » Module needs a reset method

9. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 9 System Overview Stub (to drive simulation) PL 300 ACI (AXI Configurable Interconnect) Ideal Memory (to contrast to DMC) PL 340 DMC (Dynamic Memory Controler) Wrapper Component for Your Design Second Stub and Bridge (to configure DMC)

10. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 10 Simulation Timeline