3 ObjectiveVerification and Analysis of performance parameters of a Design BlockData BandwidthLatencyEfficiencyPipelineProtocol specific parametersBus interface plugs requirementDUV
4 Performance Parameters Bandwidth :Rate of data transfer. Usually specified as KB/s, MB/s or Mb/s.Theoretical maximum bandwidth = (Data width) x (Bus Freq.)Actual Bandwidth = Amount of data transferred / Total clock cyclesExample:Clock Freq: 200 MHz , Data Bus: 4 bytesTheoretical Max Bandwidth = 200 x 4 = 800 MB/sEfficiency :number of clock cycles transferring data divided by the total number of clock cycles.Efficiency (%) =Clock cycles transferring dataTotal Clock cyclesx 100
5 Performance Parameters cont. Latency Requirements :Requests should be granted within certain cyclesRequest to response latency.Pipeline Features:Max. or Average Pending request transfersProtocol specific parameters :DDR Bus : bank BW analysis, ACT / PRECHARGE with no read/write cyclesBus Interface plugs requirements :Capable of accepting back to back requests.Capable of providing back to back responses.
6 Application Scenario 1 Cache IP Functional Specifications : Bandwidth Supported :Allegro streams : Max / Avg BW (MB/s) = 809 / 487DVD streams : Max / Avg BW (MB/s) = 474 / 245Efficiency :Reduction in number of Memory accesses = 30%Other requirements :request can be read every clock cycledata can be sent by IP every clock cycle
8 Bus Probe Internal tool - Bus probes – on STBus, AXI, DDR3 "Probes" are transaction monitors, that observe the transitions of RTL signals, recognize transactions and record them in a transaction databasePurpose :Monitor for Bus protocol compliance.Provides all transactions for scoreboarding/checking.Provides summary of transaction types along with start and end time for analysis.Provides latency, bandwidth figures.
9 Bus Probe Non-intrusive probing of the simulation Usage : A probing file defines each probe and the paths of the signals to monitorUsage :Static Mode:Need vcd/ shm database of simulation.Dynamic Mode:Reports generated on the fly during simulation run.Axi_probe <probe_name>.data_size(_value_of_attribute_data_size_).*("_common_path_and_signal_root_*_suffix_")……..OR.data_size((_value_of_attribute_data_size_).AWVALID(“testbench.awvalid").AWREADY(CONSTANT(1))…………
14 DDR Probe Efficiency of the memory Bank access analysis Compute the percentage of the maximum available bandwidth that is actually used by the DDR.global bandwidth, read / write bandwidthbandwidth per bank, read bandwidth per bank, write bandwidth per bankBank access analysisnumber of pages accessed in each bank (different row addresses)number of ACT commands per bankBus turnaroundsBus turnarounds between read transactions and write transactions, or the opposite.Sub-optimal usage of the memory banksACT followed by a PRE on the same bank, without READ nor WRITE transactionscontinuous use of a single bank (as the efficient usage of the ddr is based on alternate bank accesses)