1. Unit I Digital computer: functional units and their interconnections Mr. Mukul Varshney

2. contents Computer fundamental  Cpu  Memory  I/O devices Register Transfer Language Register Transfer Bus and Memory Transfers Mr. Mukul Varshney

3. Digital Computer It is a processing machine that process the information in digital form i.e. (0’s & 1’s). Means digital computer can only understand binary language (0’s & 1’s). If any analog quantity is to be processed, they must be converted into digital form before processing

4. Digital computer Process The block diagram of a digital computer is shown below. Whatever may be the type, size and capacity of the computer, it should have these five blocks. Input Processing Output Mr. Mukul Varshney

5. Digital Computer Functional Unit Input Devices Storage Output Unit Control Unit ALU Mr. Mukul Varshney

6. Functional units of computer The computer consists of four main parts. These are as follows: (i) Central processing unit. (ii) Memory (iii) Input Devices (iv) Output devices Mr. Mukul Varshney

7. CPU Central Processing Unit The CPU is the place where computations are performed. It is the brain and heart of a computer. CPU interprets instruction and process data contained in computer program. CPU has two component 1. ALU ( Arithmetic & Logic Unit) 2. CU ( Control Unit) The arithmetic logic unit (ALU) of the CPU performs the typical arithmetic operations such as addition, subtraction, multiplication, and division. Computers use the binary number system, to represent numbers. The binary number system has only two digits 0 and 1. Control Unit control all the operation in computer. It is the controller of the system. It also control all the devices connected to CPU. It also control the flow of data from i/p devices to memory and memory to o/p devices. Mr. Mukul Varshney

8. Memory Memory: Memory is the location where data and programs are stored while being processed by the CPU. Memory is the main storage unit in a computer. Memory consists of primary (main) memory and secondary memory. The data stored in main memory (RAM) is volatile and is erased as soon as the power supply is cut off. Therefore, secondary memory is used to store data. In secondary memory (diskettes) data is stored permanently.power supply Mr. Mukul Varshney

9. Input Devices Input Devices: Input is the process of entering and translating incoming data into machine readable form. Any hardware item which attached to the main unit of a computer that houses the CPU is referred to as peripheral device. An input device is a peripheral device through which data are entered and transformed into machine readable form. Input devices are mainly used to communicate information between humans and computer. Example: Keyboard, CPU etc. Mr. Mukul Varshney

10. Output devices Output Devices: An output device is a peripheral device that allows a computer to communicate information to humans or another machine by accepting data from the computer and transforming them into a usable form. The output devices gives the desired result to the user. Example: Monitor, Printer etc. Mr. Mukul Varshney

11. BUS

12. BUS A group of wires connecting two or more devices and providing a path to perform communication is called bus. A bus that connect major computer component such as ( CPU, Memory, I/O) is called system bus Mr. Mukul Varshney

13. Bus A bus is a set of physical connections (cables, printed circuits, etc.) which can be shared by multiple hardware components in order to communicate with one another. The purpose of buses is to reduce the number of "pathways" needed for communication between the components, by carrying out all communications over a single data channel. This is why the metaphor of a "data highway" is sometimes used. Mr. Mukul Varshney

14. Bus

15. Characteristics of a bus Characteristics of a bus A bus is characterised by the amount of information that can be transmitted at once. This amount, expressed in bits, corresponds to the number of physical lines over which data is sent simultaneously. A 32-wire ribbon cable can transmit 32 bits in parallel. The term "width" is used to refer to the number of bits that a bus can transmit at once. Additionally, the bus speed is also defined by its frequency (expressed in Hertz), the number of data packets sent or received per second. Each time that data is sent or received is called a cycle. Mr. Mukul Varshney

16. Characteristics of Bus This way, it is possible to find the maximum transfer speed of the bus, the amount of data which it can transport per unit of time, by multiplying its width by its frequency. A bus with a width of 16 bits and a frequency of 133 MHz, therefore, has a transfer speed equal to: 16 * 133.10 6 = 2128*10 6 bit/s, or 2128*10 6 /8 = 266*10 6 bytes/s or 266*10 6 /1000 = 266*10 3 KB/s or 266*10 3 /1000 = 266 MB/s Mr. Mukul Varshney

17. Kinds of bus inside the System There are three main bus groups or System bus can be separated into three functional group  ADDRESS BUS  DATA BUS  CONTROL BUS Mr. Mukul Varshney

18. Data Bus The Data Bus carries the data which is transferred throughout the system. It is bi-directional. Examples of data transfers – Program instructions being read from memory into MPU. – Data being sent from MPU to I/O port – Data being read from I/O port going to MPU – Results from MPU sent to Memory These are called read and write operations Data Bus Mr. Mukul Varshney

19. Address Bus An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer The Address Bus is used to transmit the address of the location to the memory or the I/O port. The Address Bus is unidirectional (one way): addresses are always issued by the MPU. Address Bus Mr. Mukul Varshney

20. Control Bus The Control Bus: is another group of signals whose functions are to provide synchronization (timing control) between the MPU and the other system components. Control signals are unidirectional, and are mainly outputs from the MPU. Example Control signals – RD: read signal asserted to read data into MPU – WR: write signal asserted to write data from MPU Control Bus Mr. Mukul Varshney

21. Single Bus system Mr. Mukul Varshney

22. Bus and Memory Transfer Mr. Mukul Varshney

23. contents Register Transfer Language Register Transfer Bus and Memory Transfers Mr. Mukul Varshney

24. 4-1 Register Transfer Language (RTL) Digital System: An interconnection of hardware modules that do a certain task on the information. Registers + Operations performed on the data stored in them = Digital Module Modules are interconnected with common data and control paths to form a digital computer system Mr. Mukul Varshney

25. 4-1 Register Transfer Language cont. Microoperations: is an elementry operations executed on data stored in one or more registers. For any function of the computer, a sequence of microoperations is used to describe it The result of the operation may be: ◦ replace the previous binary information of a register or ◦ transferred to another register 101101110011010110111001 Shift Right Operation Mr. Mukul Varshney

26. ADD R1,R2 Mr. Mukul Varshney

27. 4-1 Register Transfer Language cont. The internal hardware organization of a digital computer is defined by specifying:  The set of registers it contains and their function  The sequence of microoperations performed on the binary information stored in the registers  The control that initiates the sequence of microoperations Registers + Microoperations Hardware + Control Functions = Digital Computer Mr. Mukul Varshney

28. 4-1 Register Transfer Language cont. Register Transfer Language (RTL) : a symbolic notation to describe the microoperation transfers among registers Next steps: ◦ Define symbols for various types of microoperations, ◦ Describe the hardware that implements these microoperations Mr. Mukul Varshney

29. 4-2 Register Transfer (our first microoperation) Computer registers are designated by capital letters (sometimes followed by numerals) to denote the function of the register  R1 : processor register  MAR: Memory Address Register (holds an address for a memory unit)  PC: Program Counter  IR: Instruction Register  SR: Status Register Mr. Mukul Varshney

30. 4-2 Register Transfer cont. The most common way to represent a register,is by rectangle box with name of register inside The individual flip-flops in an n-bit register are numbered in sequence from 0 to n-1 (from the right position toward the left position) R1 7 6 5 4 3 2 1 0 A block diagram of a register Register R1 Showing individual bits Mr. Mukul Varshney R1

31. 4-2 Register Transfer cont. PC Numbering of bits Partitioned into two parts 150 PC(H)PC(L) 07 8 15 Lower byteUpper byte Other ways of drawing the block diagram of a register: Mr. Mukul Varshney A 16 bit register is partitioned into two parts, bit 0 through 7 are assigned the symbol L(for low byte) and 8-15 are assigned the symbol H( for high byte)

32. 4-2 Register Transfer cont. Information transfer from one register to another is described by a replacement operator: R2 ← R1 This statement denotes a transfer of the content of register R1 into register R2 The transfer happens in one clock cycle The content of the R1 (source) does not change The content of the R2 (destination) will be lost and replaced by the new data transferred from R1 We are assuming that the circuits are available from the outputs of the source register to the inputs of the destination register, and that the destination register has a parallel load capability Mr. Mukul Varshney

33. 4-2 Register Transfer cont. 4-2 Register Transfer cont. Conditional transfer occurs only under a control condition Representation of a (conditional) transfer P: R2 ← R1 A binary condition (P equals to 0 or 1) determines when the transfer occurs The content of R1 is transferred into R2 only if P is 1 Mr. Mukul Varshney

34. 4-2 Register Transfer cont. n Clock R1 R2 Control Circuit Load tt+1 Clock Load Transfer occurs here Synchronized with the clock P Hardware implementation of a controlled transfer: P: R2 ← R1 Block diagram: Timing diagram Mr. Mukul Varshney

35. 4-2 Register Transfer cont. Mr. Mukul Varshney Unconditional R1 ← R2 Conditional P:R1 ← R2 Simultaneous R1 ← R2, R3 ← R2

36. SIMULTANEOUS OPERATIONS If two or more operations are to occur simultaneously, they are separated with commas P: R3  R5,, MAR  IR Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the contents of register IR into register MAR

37. 4-2 Register Transfer cont. Basic Symbols for Register Transfers SymbolDescriptionExamples Letters & numerals Denotes a registerMAR, R2 Parenthesis ( ) Denotes a part of a register R2(0-7), R2(L) Arrow ←Denotes transfer of information R2 ← R1 Comma,Separates two microoperations R2 ← R1, R1 ← R2 Mr. Mukul Varshney

38. 4-2 Register Transfer cont. Q1.Show the H/W implementation to the given statement T1 = B A T2 = B C Q1.Show the H/W implementation to the given statement xy : A B, B A Mr. Mukul Varshney

39. 4-2 Register Transfer cont. Mr. Mukul Varshney Every statement written in a register transfer notation implies a H/W construction for implementing the transfer. The internal H/W organization of a digital computer is best defined by specifying : 1.The set of register it contains. 2.Sequence of micro-operation performed on the binary information stored in the register. 3.The control that initiates the sequence of micro-operation.

40. 4-3 Bus and Memory Transfers A shared communication path consisting of one or more connection lines is known as bus Bus transfer : The transfer of data through bus is known as bus transfer. Memory Transfer : When a data is read from memory or is stored in memory is referred to as memory transfer. Mr. Mukul Varshney

41. 4-3 Bus and Memory Transfers Paths must be provided to transfer information from one register to another A Common Bus System is a scheme for transferring information between registers in a multiple-register configuration A bus: set of common lines, one for each bit of a register, through which binary information is transferred one at a time Control signals determine which register is selected by the bus during each particular register transfer Mr. Mukul Varshney

42. 4-3 Bus and Memory Transfers 3 2 1 0 Register D D 3 D 2 D 1 D 0 3 2 1 0 Register C C 3 C 2 C 1 C 0 3 2 1 0 Register B B 3 B 2 B 1 B 0 3 2 1 0 Register A A 3 A 2 A 1 A 0 D 3 C 3 B 3 A 3 S0S0 S1S1 MUX3 3 2 1 0 D 2 C 2 B 2 A 2 S0S0 S1S1 MUX2 3 2 1 0 D 1 C 1 B 1 A 1 S0S0 S1S1 MUX1 3 2 1 0 D 0 C 0 B 0 A 0 S0S0 S1S1 MUX0 3 2 1 0 4-Line Common Bus Register ARegister BRegister CRegister D Bus lines Mr. Mukul Varshney

43. 4-3 Bus and Memory Transfers A bus system with multiplexer: For k register of n bits, each produce an n– line common bus. The number of multiplexer needed is equal to n( no of bits in each register) The size of each multiplexer must be k × 1 Mr. Mukul Varshney

44. 4-3 Bus and Memory Transfers The transfer of information from a bus into one of many destination registers is done: ◦ By connecting the bus lines to the inputs of all destination registers and then: ◦ activating the load control of the particular destination register selected We write: R2 ← C to symbolize that the content of register C is loaded into the register R2 using the common system bus It is equivalent to: BUS ← C, (select C) R2 ← BUS (Load R2) Mr. Mukul Varshney

45. 4-3 Bus and Memory Transfers: Three- State Bus Buffers A bus system can be constructed with three-state buffer gates instead of multiplexers A three-state buffer is a digital circuit that exhibits three states: logic-0, logic-1, and high-impedance (Hi-Z) Normal input A Control input C Three-State Buffer Output B Mr. Mukul Varshney

46. 4-3 Bus and Memory Transfers: Three- State Bus Buffers cont. A C=1 B A B A C=0 B A B Buffer Open Circuit Mr. Mukul Varshney

47. TRANSFER FROM BUS TO A DESTINATION REGISTER Three-State Bus Buffers Bus line with three-state buffers Reg. R0Reg. R1Reg. R2Reg. R3 Bus lines 2 x 4 Decoder Load D 0 D 1 D 2 D 3 z w Select E (enable) Output Y=A if C=1 High-impedence if C=0 Normal input A Control input C Select Enable 0 1 2 3 S0 S1 A0 B0 C0 D0 Bus line for bit 0

48. 4-3 Bus and Memory Transfers: Three- State Bus Buffers cont. 2×4 Decoder Select Enable 0 1 2 3 S1S1 S0S0 E Bus line for bit 0 A0A0 B0B0 C0C0 D0D0 Bus line with three-state buffer (replaces MUX0 in the previous diagram) Mr. Mukul Varshney

49. 2 X 4 DECODER Output for 0 bit Output for bit 1 A0 A1 B1B1 B0B0 C1C1 C0C0 D1D1 D0D0 Mr. Mukul Varshney

50. 4-3 Bus and Memory Transfers: Memory Transfer Memory read : Transfer from memory Memory write : Transfer to memory Data being read or wrote is called a memory word (called M)- (refer to section 2-7) It is necessary to specify the address of M when writing /reading memory This is done by enclosing the address in square brackets following the letter M Example: M[0016] : the memory contents at address 0x0016 Mr. Mukul Varshney

51. 4-3 Bus and Memory Transfers: Memory Transfer cont. Assume that the address of a memory unit is stored in a register called the Address Register AR Lets represent a Data Register with DR, then: Read: DR ← M[AR] Write: M[AR] ← DR Mr. Mukul Varshney

52. 4-3 Bus and Memory Transfers: Memory Transfer cont. AR x12 x0C x0E x10 x12 x14 x16 x18 19 34 45 66 0 13 22 R1 ← M[AR] R1 100 R1 66 RAM R1 100 Mr. Mukul Varshney