0. Registers and Counters
UNIT 12
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1. Registers(暫存器)與Counters(計數器):
在一般的計算機中，暫存器被廣泛使用在記憶體以外的”暫時資料儲存”。因此對於CPU
等模組提供相互間的資料轉移、基礎運算。而計數器主要用來進行循序電路在處理工作上
的排序，以時序脈波(clock)來控制信號。

2. 4-Bits D-FF Register
Figure Bit D Flip-Flop Registers with Data, Load, Clear, and Clock Inputs
This register has a load signal that ANDed the clock.
When Load=0, register not clocked……hold the present value.
when Load=1, the data will be load into the FF on the falling edge of the Clk
3. For example, if Q outputs are (0000) and Data is (1101). when load=1, the output
Q change to 1101 after falling edge clock.
4. However, this design with gating the Clk will lead to a timing problems.

3. To avoid the timing issue, the signals are connected to become a common input
When Load =1, the Clk is enable, then D input will be loaded into the output Q
With a bus notation.

4. Figure 12.2 Data Transfer Between Registers
The Data transfer between Registers
Figure 12.2 Data Transfer Between Registers
When En=1, Load=1, the data in A will store in Q after the rising edge of the clock.
When En=0, load=1, the data in B will store in Q.

5. Figure 12.3 Logic Diagram for 8-Bit Register with Tri-State Output
A 8-bit register and how data transfer by using tri-state bus
Figure 12.3 Logic Diagram for 8-Bit Register with Tri-State Output
When EnA=0, A are output to
bus, when LdG=1, data is load
into register G
Use a decoder to select
data transfer:

6. Figure 12.5 n-Bit Parallel Adder with Accumulator
A n-bits parallel adder with accumulator
Figure 12.5 n-Bit Parallel Adder with Accumulator
To store one number(Xi) in a register of FF(called accumulator), and add a second
Number(Yi) to it, leaving the results stored in the accumulator.
Process:
ClrN
Store Xi in Accumulator register (Ad, CLK)
Load adders input Yi, Si = Xi + Yi (Ad, CLK)

7. Figure 12.6 Adder Cell with Multiplexer
Select Yi or Si into a register by a MUX : it is complex!!
Figure 12.6 Adder Cell with Multiplexer

8. Figure 12.7 Right-Shift Register
A shift register in which binary data can be stored and this data can be shifted to
The left or right when shift signal is applied.
The initial register is 0101
When Series input(1101) loaded
The sequence of the shift register
Is : 0101
1010
1101
0110
1011
Right-shift

9. Figure 12.8 8-Bit Serial-in, Serial-out Shift Register
Shift registers: Serial-in Serial out:
Figure Bit Serial-in, Serial-out Shift Register

10. Figure 12.10 Parallel-in, Parallel-Out Right Shift Register
Shift registers: Parallel-in and Parallel-out
Figure Parallel-in, Parallel-Out Right Shift Register

11. Table 12.1 Shift Register Operation
Shift registers: Parallel-in and Parallel-out : two input control
Table 12.1 Shift Register Operation 1 1 1 1

12. Figure Shift Register
A shift register with inverted feed back is often called a Johnson counter
initial 000,D3= 1, then it become 100(and then 110,111,011….)
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13. Figure 12.13 Synchronous Binary Counter
Asynchronous Counter: 非同步二進制計數器又稱為漣波計數器(Ripple counter)
Figure Synchronous Binary Counter
第一級的輸出狀態改變後，後一級才會有動作。
因此若連續加時脈信號到第一級FF Clk, 則會進行一非同步的計數工作。
N 個FF的非同步計數器，可以計數範圍由0~2n-1為止。舉例來說, 下面可計數0-15
J=K=1, 遇到負緣觸發, 狀態反相
當FF的級數增加，而輸入時序脈波頻率很高
，發生後一級正反器狀態還沒改變，下一時序
脈波又再度送入第一級，導致計數錯誤。
這是非同步計數的缺點。

14. Synchronous Counter: 同步二進制計數器
T-FF: 當T=1, 轉態(0變1, 1變0)

15. Figure 12.14 Kanaugh Maps For Binary Counter
TA=1
TB=A
Tc=BA

16. Figure 12.15 Binary Counter with D Flip-Flops
Synchronous Counter: 同步二進制計數器: convert T-FF to a D-FF
By adding XOR gate.
Figure Binary Counter with D Flip-Flops
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17. Figure 12.16 Kanaugh Maps for D Flip-Flops
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18. Figure 12.17 State Graph and Table Up-Down Countre
UP-down binary counter
Figure State Graph and Table Up-Down Countre
Up counter (U=1, D=0)
Down counter
(U=0, D=1)

19. Figure 12.18 Binary Up-Down Counter
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20. Figure 12.19 Loadable Counter with Count Enable
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21. Figure 12.20 Circuit for Figure 12.19
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22. Figure 12.21 State Graph for Counter
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23. Table 12.3 State Table for Figure 12.21
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24. Figure 12.22
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25. Table 12.4 Input for T Flip-Flop
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26. Figure 12.23 Counter Using T Flip-Flops
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27. Figure 12.24 Timing Diagram for Figure 12.23
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28. Figure 12.25 State Graph for Counter
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29. Figure 12.26 Counter of Figure 12.21 Using D Flip-Flops
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30. Table 12.5 S-R Flip-Flops Inputs
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31. Table 12.6
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32. Figure 12.27 Counter of Figure 12.21 Using S-R Flip-Flops
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33. Table 12.7 J-K Flip-Flop Inputs
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34. Table 12.8
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35. Table 12.9 Determination of Flip-Flop Input
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36. Figure 12.28 Counter of Figure 12.21 Using J-K Flip-Flops
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37. Figure 12.29 Derivation of Flip-Flop Input
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38. Images From End of Chapter Problems Problem 12.1
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