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1 第八章 正反器及其相關元件 Flip-Flops and Related Devices 1.Latches 栓鎖電路 2.Edge-Triggered Flip-Flops 邊緣觸發正反器 3.Master-Slave Flip-Flops 主從式正反器 4.Flip-Flop Operating.

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Presentation on theme: "1 第八章 正反器及其相關元件 Flip-Flops and Related Devices 1.Latches 栓鎖電路 2.Edge-Triggered Flip-Flops 邊緣觸發正反器 3.Master-Slave Flip-Flops 主從式正反器 4.Flip-Flop Operating."— Presentation transcript:

1 1 第八章 正反器及其相關元件 Flip-Flops and Related Devices 1.Latches 栓鎖電路 2.Edge-Triggered Flip-Flops 邊緣觸發正反器 3.Master-Slave Flip-Flops 主從式正反器 4.Flip-Flop Operating Characteristics 正反器運作特性 5.Flip-Flop Applications 正反器的用途 6.One-Shots 單擊 ( 單觸發 ) 7.The 555 Timer (555 定時器 ) 8.Troubleshooting 檢修 9.Programmable Logic 可程式邏輯 10.Digital System Application 數位系統的應用

2 2 8-1 Latches 栓鎖電路 Active High, Active Low S-R Latch Contact Bounce Gated S-R Latch Gated D Latch

3 3 Figure 8--1 Two versions of SET-RESET (S-R) latches. Open file F08-01 and verify the operation of both latches. Thomas L. Floyd Digital Fundamentals, 8e 1.Latches 栓鎖電路 Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

4 4 Figure 8--2 Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b). Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路

5 5 Figure 8--3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition. 1.Latches 栓鎖電路 原來 Q 是 0, 脈 波來之後 Q 變 成 1 原來 Q 是 1, 脈 波來之後 Q 變 成 0 原來 Q 是 1, 脈波來之後 Q 不變 原來 Q 是 0, 脈波來之後 Q 不變 當輸入端都 是 1 時, 輸出 不變 當輸入端同 時由 0 變成 1 時, 輸出的值 不確定

6 6 Figure 8--4 Logic symbols for the S-R and S-R latch. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路

7 7 Figure 8--5 Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路 例題 8-1 若將圖 8-5(a) 的波形加到圖 8-4(b) 的輸入端, 試繪出其 輸出波形, 假設輸出端 Q 的起始值為 0.

8 8 Figure 8--6 The S-R latch used to eliminate switch contact bounce. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路

9 9 Figure A--13 The 74LS279 quad S-R latch. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路

10 10 Figure 8--7 A gated S-R latch. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路

11 11 Figure 8--8 Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路 例題 8-2 若將圖 8-9(a) 的波形加到圖 8-8 的輸入端, 試繪出其輸 出波形, 假設該 Gated S-R Latch 的起始狀態為 RESET.

12 12 Figure 8--9 A gated D latch. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路

13 13 Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路 例題 8-3 若將圖 8-11(a) 的波形加到圖 8-10 的輸入端, 試繪出其 輸出波形, 假設該 Gated D Latch 的起始狀態為 RESET.

14 14 Figure A--14 The 74LS75 quad gated D latches. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 1.Latches 栓鎖電路

15 15 Figure Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered). Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器 正緣 觸發 負緣 觸發 加圓 圈 表示邊緣觸發

16 Edge-Triggered Flip-Flops 邊緣觸發正反器 正緣觸發, 負緣觸發 邊緣觸發脈波產生器 邊緣觸發 S-R 正反器 邊緣觸發 D 型正反器 邊緣觸發 J-K 正反器 具有非同步的 Preset 及 Clear 端之 J-K 正反器

17 17 Figure Operation of a positive edge-triggered S-R flip-flop. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

18 18 例題 8-4 若將圖 8-16(a) 的波形加到圖 8-15 的輸入端, 試繪出其 輸出波形 Q 及 Q, 假設該正緣觸發的 S-R 正反器之起始狀態為 RESET. Figure Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器 Figure 8--14

19 19 Figure Edge triggering. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

20 20 Figure Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

21 21 Figure Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

22 22 Figure A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器 D Flip-Flop = S-R Flip-Flop + Invertor

23 23 例題 8-5 若將圖 8-21(a) 的波形加到一個正緣觸發的 DFF 之輸入 端, 試繪出其輸出波形 Q, 假設該正緣觸發的 D 型正反器之起始 狀態為 RESET. Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

24 24 Figure A simplified logic diagram for a positive edge-triggered J-K flip-flop. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

25 25 Figure Transitions illustrating the toggle operation when J =1 and K = 1. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

26 26 Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器 例題 8-6 若將圖 8-24(a) 的波形加到一個負緣觸發的 JKFF 之輸 入端, 試繪出其輸出波形 Q, 假設該負緣觸發的 JK 型正反器之 起始狀態為 RESET.

27 27 Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器 例題 8-7 若將圖 8-25(a) 的波形加到一個正緣觸發的 JKFF 之輸 入端, 試繪出其輸出波形 Q, 假設該正緣觸發的 JK 型正反器之 起始狀態為 RESET.

28 28 Figure Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器 非同步的 Preset 及 Clear 端

29 29 Figure Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Edge-Triggered Flip-Flops 邊緣觸發正反器

30 30 Figure Open file F08-28 to verify the operation. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器 例題 8-8 若將圖 8-28(a) 的波 形加到一個具有 Preset 及 Clear 端的正緣觸發的 JKFF 之 輸入端, 試繪出其輸出波形 Q, 假設該正緣觸發的 JK 型正 反器之起始狀態為 RESET.

31 31 Figure A--15 Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flops. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

32 32 Figure A--16 Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flops. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器

33 33 Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器 例題 8-9 若將圖 8-31(a) 的波形加到 74HC112 的其中一個負緣 觸發的 JKFF 之輸入端, 試繪出其輸出波形 Q, 假設該負緣觸發 的 JK 型正反器之起始狀態為 RESET.

34 34 Figure Basic logic diagram for a master-slave J-K flip-flop. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 3. Master-Slave Flip-Flops 主從式正反器 8-3 Master-Slave Flip-Flops 主從式正反器

35 35 Figure Pulse-triggered (master-slave) J-K flip-flop logic symbols. 3. Master-Slave Flip-Flops 主從式正反器 資料在 Clock 正緣來的時候被載入, 而在 Clock 負緣來的時候輸出 資料在 Clock 負緣來的時候被載入, 而在 Clock 正緣來的時候輸出

36 36 Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 3. Master-Slave Flip-Flops 主從式正反器 例題 8-10 若將圖 8-34(a) 的波 形加到一個主從式的 JKFF 之 輸入端, 試繪出其輸出波形 Q, 假設該主從式的 JK 型正反 器之起始狀態為 RESET.

37 37 Propagation Delay Times 極際延遲時間 Set-up Time 建立的時間 Hold Time 維持的時間 Maximum Clock Frequency 最高鐘脈波頻率 Pulse Width 脈波寬度 Power Dissipation 功率消耗 8-4. 正反器的運作特性 Flip-Flop Operating Characteristics

38 38 Figure Propagation delays, clock to output. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 4.Flip-Flop Operating Characteristics 正反器運作特性

39 39 Figure Propagation delays, preset input to output and clear input to output. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 4.Flip-Flop Operating Characteristics 正反器運作特性

40 40 Figure Set-up time (t s ). The logic level must be present on the D input for a time equal to or greater than t s before the triggering edge of the clock pulse for reliable data entry. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 4.Flip-Flop Operating Characteristics 正反器運作特性

41 41 Figure Hold time (t h ). The logic level must remain on the D input for a time equal to or greater than t h after the triggering edge of the clock pulse for reliable data entry. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 4.Flip-Flop Operating Characteristics 正反器運作特性

42 Flip-Flop Applications 正反器的用途 並聯資料暫存器 除法器 除 4 電路, 除 8 電路 用正反器來產生二進制的計數順序

43 43 Figure Example of flip-flops used in a basic register for parallel data storage. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 5. Flip-Flop Applications 正反器的用途 並聯資料暫存器

44 44 Figure The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 5. Flip-Flop Applications 正反器的用途 除法器

45 45 Figure Example of two J-K flip-flops used to divide the clock frequency by 4. Q A is one-half and Q B is one-fourth the frequency of CLK. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 5. Flip-Flop Applications 正反器的用途 除 4 電路

46 46 例題 8-11 試繪出圖 8-42 f out 的輸出波 形, 若將一個 8KHz 的方波加到圖 8-42 的 f in, 假設該正緣 觸發的 JK 型正反器 之起始狀態為 RESET. Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 5. Flip-Flop Applications 正反器的用途 除 8 電路 Figure 8--39

47 47 Figure Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 5. Flip-Flop Applications 正反器的用途 用正反器來 產生二進制 的計數順序

48 48 Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 5. Flip-Flop Applications 正反器的用途 Figure 例題 8-12 試繪出 圖 8-45 中的 CLK 與 Q A,Q B,Q C 的 波形關係, 並用 二進制表示該組 輸出波型.

49 One-Shots 單擊器 ( 單觸發 ) 簡單的單擊器 Mono-stable Multivibrator 單穩態多諧震盪器 Non-retriggerable one-shot 不可再觸發的單擊器 Retriggerable one-shot 不可再觸發的單擊器

50 50 Figure A simple one-shot circuit. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 6. One-Shots 單擊 ( 單觸發 )

51 51 Figure Basic one-shot logic symbols. CX and RX stand for external components. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 6. One-Shots 單擊 ( 單觸發 )

52 52 Figure Nonretriggerable one-shot action. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 6. One-Shots 單擊 ( 單觸發 ) 這些脈波將被忽略

53 53 Figure Retriggerable one-shot action. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 6. One-Shots 單擊 ( 單觸發 ) 重新計時

54 54 Figure A sequential timing circuit using three one-shots. Thomas L. Floyd Digital Fundamentals with VHDL Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 6. One-Shots 單擊 ( 單觸發 )

55 The 555 Timer (555 定時器 ) 555 的內部方塊圖 用 555 作成單擊器 用 555 作成不穩態多諧震盪器 改善 555 的 Duty Cycle

56 56 Figure Internal functional diagram of a 555 timer (pin numbers are in parenthesis). Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 7. The 555 Timer (555 定時器 )

57 57 Figure The 555 timer connected as a one-shot. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 7. The 555 Timer (555 定時器 )

58 58 Figure One-shot operation of the 555 timer. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 7. The 555 Timer (555 定時器 ) 平常 觸發後電容 器開始充電 電容器充到 超過 Thresh 電壓, 正反器 被 Reset, 電 晶體導通, 電 容器急速放 電

59 59 Figure The 555 timer connected as an astable multivibrator (oscillator). Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 7. The 555 Timer (555 定時器 ) 不穩態多諧震盪器

60 60 Figure Operation of the 555 timer in the astable mode. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 7. The 555 Timer (555 定時器 )

61 61 Figure Frequency of oscillation as a function of C 1 and R 1 1 2R 2. The sloped lines are values of R 1 1 2R 2. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 7. The 555 Timer (555 定時器 )

62 62 Figure The addition of diode D 1 allows the duty cycle of the output to be adjusted to less than 50 percent by making R 1, R 2. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 7. The 555 Timer (555 定時器 ) 由於充電時, 電流 經過 R1 及 R2, 但放 電時, 電流只經過 R2, 因此輸出波形 並不對稱, 可加 Diode 改進.

63 63 Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 7. The 555 Timer (555 定時器 ) 例題 8-16 如圖 8-55 所示為一個 555 的不穩態多諧震盪器, 試算出其輸出頻率及 Duty Cycle. Sol: f = 1.44/(R 1 +2R 2 )C 1 = 5.64KHz Duty Cycle = ((R 1 +R 2 )/(R 1 +2R 2 ))100% = 59.5%

64 64 Figure A--18 Three ways to set the pulse width of a 不可再觸發的單擊器 Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. t w = 30nst w = 0.7(2kΩ)C EXT t w = 0.7R EXT C EXT 6. One-Shots 單擊 ( 單觸發 )

65 65 Figure A--19 Logic symbol for the 74LS122 retriggerable one-shot. 可再觸發的單擊器 Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 6. One-Shots 單擊 ( 單觸發 )

66 66 Figure A--19 Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 例題 A-1 在某些應用裡, 我們需要一個脈波寬度大約 100ms 的單擊器, 試用一個 來設計, 並列出各零件的數值. SOL: 隨意選用一個 39KΩ 的電 阻, t w = 0.7R EXT C EXT, C EXT = t w / 0.7R EXT = 100x10 -3 S/0.7(39K Ω) = 3.66x10 -6 F = 3.66 μF 若電容一定要用 3.3 μF, t w = 0.7R EXT C EXT, R EXT = t w / 0.7 C EXT = 43.29KΩ 因此可選用一個 39KΩ 的電阻再串 接一個 5KΩ 的可變 電阻來微調. 6. One-Shots 單擊 ( 單觸發 )

67 67 Figure Two-phase clock generator with ideal waveforms. Open file F08-64 and verify the operation. 雙相位鐘脈波產生器 Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 8-8 Troubleshooting 檢修

68 68 Figure Logic analyzer displays for the circuit in Figure Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 8. Troubleshooting 檢修

69 69 Figure Two-phase clock generator using negative edge-triggered flip-flop to eliminate glitches. Open file F08-66 and verify the operation. Thomas L. Floyd Digital Fundamentals, 8e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. 改用負緣 觸發的正 反器可改 善 Glitch 現 象 8. Troubleshooting 檢修


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