1. 1/1/ / faculty of Electrical Engineering eindhoven university of technology 5Z008: Microprocessor design Introduction to the ‘Interactive Design and Simulation System’: ‘IDaSS’

2. 1/1/ / faculty of Electrical Engineering eindhoven university of technology What are we going to do here ? Tell a story –Introduction: what is IDaSS –The parts: schematics, blocks, connectors, buses –IDaSS as abstract ‘switching technology’ –What is in the ‘IDaSS-OGO’ package Do-it-yourself demo: create a running light Demo: synthesis of running light in FPGA box

3. 1/1/ / faculty of Electrical Engineering eindhoven university of technology What is IDaSS ? Design tool for complex digital systems –‘Register Level’: storing & handling of N-bit values –‘Synchronous’: one ‘system clock’ for all flip-flops –Schematics for structure, texts for (complex) behaviour Interactive simulation of the system under design –Design modifications simulated immediately –Inspecting and modifying system state is very simple –‘Design a little, test a little’ approach is possible Coupling to other (commercial) tools is available

4. 1/1/ / faculty of Electrical Engineering eindhoven university of technology UVHMPRL Schematics: the ‘backbone’ of IDaSS Top-level schematic Sub- schematic X Sub- schematic Y AB (normal) block XY Sub- schematic symbol Sub-schematic X\L Re-used as sub- schematic Y\M ‘edit’ Same design, different states !

5. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Blocks and connectors The ‘Basic Building Blocks’ do the actual work –Store data with registers and memories –Modify data with ‘operator’ blocks –Control the system with ‘state controllers’ Different types of connectors possible –Every type its own symbol within block on schematic Normal input Continuous output C Control input ‘Three-state’ output: ‘disabled’ ‘enabled’ ‘unknown’ Does not output a value on a bus Outputs a value on a bus Outputs unknown value on a bus

6. 1/1/ / faculty of Electrical Engineering eindhoven university of technology SUB Sub-schematic symbol ‘SUB’ Within actual schematic ‘SUB’: Buses Transport values between blocks –All attached connectors the same number of bits ! –Just one transport per bus and clock cycle –Special values: ‘Three-State’, ‘UNKnown’, OVerLoad’ Can break through sub-schematic boundaries D D Bi-directional connector ‘D’Connector block ‘D’ with bi-directional connector Direct connection between buses

7. 1/1/ / faculty of Electrical Engineering eindhoven university of technology From logic gate to ‘operator’ block Variable number of in- and outputs One or more ‘functions’ to execute –Each should get a different name, name choice is free –One of the functions is executed ‘by default’ –Other functions can be chosen by ‘state controller’ Functions described as set of (text!) expressions –Assign values to outputs, based on inputs and constants –More than 60 arithmetic/logic basic operations –No feedback possible: combinatorial functions only

8. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Intermezzo: IDaSS expressions Assign with := and separate with. Three types of operators in use –‘Unary’: out := in not. –‘Binary’: out := inA /\ inB. “AND” –‘Keyword’: out := in from: 0 to: 3. Order: first unary, then binary, then keyword –Unary and binary strictly from left to right ! –Keyword operators separated with normal braces () –Normal braces as usual to modify order of execution In IDaSS: type [F 1 ], then click ‘subjects’

9. 1/1/ / faculty of Electrical Engineering eindhoven university of technology From flip-flop to ‘register’ Register is set of Flip-Flops which ‘belong together’ –Jointly store an N-bits value (N = 1..64) –Can be initialised to a specific value upon systeem reset –Can be loaded with new value once per clock cycle –Controlled by commands coming from state controller ‘ hold ’: keep the already loaded value ‘ load ’: load a new value from the input connector ‘ inc ’/’ dec ’: increment/decrement the old value by one –One of the commands can be chosen as ‘default’ –Output connector outputs current value

10. 1/1/ / faculty of Electrical Engineering eindhoven university of technology From FSM to ‘state controller’ Central control for system (parts) One or more states with separate text descriptions WaitLeft: COUNTER inc; [ COUNTER = 0 | 1 “Counter at 0, change local state:” -> ShiftLeft ]; << Colon is required here ! Send command ‘inc’ to block ‘COUNTER’ Semicolon separates commands State name Start test block Test- expression Start test- ’branch’ Test-value(s) End test block ‘Go to…’ ‘remain in this state’ Name of next state When executing ‘ -> ’, remainder is not evaluated !

11. 1/1/ / faculty of Electrical Engineering eindhoven university of technology What is in the IDaSS-OGO package Special version of IDaSS for OGO 1.2 –Complete IDaSS system VHDL generator removed (not needed here) Verilog generator adapted for Xilinx WebPACK –Automatic initialisation of Xilinx Verilog generator Extra files in ‘designs\ogo’ folder –‘asm_ogo.com’ assembler for OGO processor –‘isatest.asm’ test program for OGO processor –‘ogo_al.des’ IDaSS simulation of OGO processor See file ‘instalOGO.txt’ !

12. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Do-it-yourself demo time… Last chapter of IDaSS manual… –Register + operator + state controller = running light –Execute step by step in groups of 2 or 3 Prepare for running in the FPGA box –Build in a sub-schematic (‘add block’, ‘schematic’) –Bring register value to the ‘outside world’ Connector block on subschematic + connector on symbol –Extra register to divide 24 MHz to  6 Hz How many bits ? Every clock cycle ‘ inc ’ or ‘ dec ’ ! State controller steps running light when register equals zero

13. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Conversion to FPGA Clock and system reset connected automatically –System reset is top-left pushbutton on box Connect outputs to LED bar display –Use ‘properties…’ of connector in connector block Add ‘BUSDRIVE’ with value 24 (mA) Add ‘BUSOUTTYPE’ with value ‘switch’ Add ‘BUSLOC’ with value 57 (‘pin index’ van LED 1) Schematic symbol ‘file out’, ‘to Spartan-II Verilog’ –Store files in WebPACK ‘project directory’ –In WebPACK, use ‘project’, ‘add source’ See files ‘spartan2.pdf’ and ‘fpgaconn.doc’ in IDaSS ‘support’ folder !