1. Project Review Meeting Catania, Nov.09-10, 2010 15/09/2015 1 MODERN ENIAC WP2 Meeting WP2 Tasks review summary Catania, 2010 Nov. 09-10

2. Contents WP2 Task 2.1 to 2.5 summary Matrix, Gantt chart, relation with other Wps Action points from meeting Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 2

3. 3 MODERN General Meetings Catania, Nov. 9 & 10, 2010 3 WP2: Relationship among work packages

4. Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 4 WP2 Objectives Objectives Provide a chain of TCAD simulations tools which enable simulation of the impact of process variations and reliability on device level, including compact models and mixed mode device/circuit simulation Assess the impact of process and device variations for relevant technologies, mainstream planar bulk CMOS down to 45/32nm, new device architectures on bulk & on SOI suitable for 22nm, NVM technologies, and non- silicon technologies Compare simulation results with hardware and calibrate them on hardware to verify PV methodology and to foster physical understanding of major sources of PV in above technologies

5. 15/09/2015 5 5 WP2 Key Figures 5 Tasks/18 deliverables (reports): –Process (2) & device (6) simulation –Electrical characterization (4) & Reliability(3) –Compact modeling (3) –Covering both Tools/Methodology improvements and Application results Wide spectrum of technologies & devices applications –45nm: planar Mosfet –32nm: planar Mosfet, FinFet –22nm: FD SOI Mosfet –State-of-art NVM –Discrete Power Device, SiC, GaN/AlGaN –HV CMOS TOTAL EFFORT: 638.6 PM =53.22 PY Reference: MODERN Rev2.1.7 project description Project Review Meeting Catania, Nov.09-10, 2010

6. 6 WP2 meeting Domain overview per task and partner MODERN General Meetings Catania, Nov. 9 & 10, 2010 Technologi es Process simulation Device simulation Electrical Charact. ReliabilityCompact Modeling Task2.12.22.32.42.5 HVMOSAMS TUW Planar CMOS65nmUNCA 45nmUNGL POLI SNPS (STF2) IMEP STF2UNGLUNGL POLI STF2 NXP 32nmUNGL POLI (STF2) IMEP STF2UNGL NVM41nmUNET NMX SNPS UNET NMXUNET (NMX)UNET NMX FDSOIIMEP (STF2)LETI IMEPLETI Finfets, MUG, GAA STF2NXPIMEP SiC Power MOS STI AlGaN-GaN HEMT STI PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1). Significant communalities of technology targets, except different ones for Process and Device simulation. (not funded)

7. 15/09/2015 7 7 WP2 Task Definition and Contributors WP2Process/Device to Compact ModelingContributors T2.1PV aware process simulationST-I, AMS, TUW T2.2PV aware device simulation UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS T2.3 Electrical characterization of PV, software (TCAD) / hardware comparison & calibration NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I T2.4 Correlation between PV and reliability, reliability modeling AMS, IMEP, UNET, TUW, UNCA, UNGL T2.5PV aware compact modeling UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNG Project Review Meeting Catania, Nov.09-10, 2010

8. 15/09/2015 8 8 WP2 Task Leaders WP2STF2Andre.Juge@st.com T2.1ST-Ivaleria.cinnera@st.com T2.2UNGLa.asenov@elec.gla.ac.uk T2.3NXPhans.tuinhout@nxp.com T2.4AMSJong-mun.park@austriamicrosystems.com T2.5UNETpaolo.pavan@unimore.it

9. Contents WP2 introduction Task 2.1 to 2.5 summary Matrix, Gantt chart, relation with other Wps Action points from meeting Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 9

10. MODERN General Meeting Task 2.1 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010 15/09/2015 10

11. 15/09/2015 11 15/09/2015 11 Process simulation: T2.1 Deliverables RefDeliverable/ ContributorsDue date D2.1.1First process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) M15 Done D2.1.2Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) M27 Task Leader: valeria.cinnera@st.com

12. 12 MODERN General Meetings Catania, Nov. 9 & 10, 2010 ST-I WP2 Activity High Level factory Process recipes Specific process conditions Mask Layout Process flow Virtual device TCAD Experiments Process Compact model derived from TCAD PCM FAB1 FAB2 Technology transferred to FAB2 using PCM

13. 13 MODERN General Meetings Catania, Nov. 9 & 10, 2010 13 PCM approach Parameter screening to identify the process parameters that have an important impact on target electrical parameters. Parameterized simulation setup (DOE) generating several simulation runs. Device simulations of breakdown and I-V characteristic for each experiment. Extraction of RSM model of device characteristics as function of process parameters using PCM Studio. D OE EHD5 SEMICELL SENTAURUS WORKBENCH PCM STUDIO PCM Synopsys platform: Sentaurus and PCM Studio Simulation of Power-Mos semi cell with the nominal values of the process input parameters

14. 14 MODERN General Meetings Catania, Nov. 9 & 10, 2010 Process Variation at AMS - TUW Process Flow Parameters Sentaurus Work Bench Minimos Parameter Extraction Correlation Interface between commercial Synopsys Process Simulator and Minimos Device Simulator

15. WP2 T2.1 action items Task 2.1: Process simulation –D2.1.2 (M27): « Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) »  AI (STI, AMS, M27): HVMOS and AsGaN-SiC device sensitivity analysis to Process variations to be validated on HW data available from D2.3.2 Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 15

16. MODERN General Meeting Task 2.2 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010 15/09/2015 16

17. 15/09/2015 17 15/09/2015 17 Device Simulation: T2.2 Deliverables RefDeliverable/ ContributorsDue date D2.2.1Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools (UNGL) M6 D2.2.2Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies, and Discrete Power Device,SiC, GaN/AlGaN technologies. Prototype implementation of the treatment of individual dopants and traps in the device modeling tools (UNGL, UNET, NXP, ST-I, SNPS) M12 D2.2.3Device simulation analysis of dominant variability sources in state of-the-art Non- Volatile-Memory technologies (UNET, UNGL, NMX, SNPS) M18 D2.2.4Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET). Efficient compact model extraction procedures for modeling process variations and device fluctuations (NXP, UNET, POLI) M24 D2.2.5Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations (UNET) TCAD based assessment of PV effects of potential 22nm device architectures (UNGL) M27 D2.2.6Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET) Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2) M36 Task Leader: a.asenov@elec.gla.ac.uk

18. T2.2.2 Overview V D =50mV V D =1.0V 18 15/09/2015 V D =50mV V D =1.0V

19. 15/09/2015 19 15/09/2015 19 T2.2.2 Overview 15/09/2015 (UNET-Università di Udine)(Synopsys)

20. 15/09/2015 20 15/09/2015 20 T2.2.2 Overview 15/09/2015 (UNET-Università di Bologna)

21. 15/09/2015 21 15/09/2015 21 T2.2.3 Overview [V]σV T [mV] RDD (Glasgow) 1.02141 RDD (Numonyx) 1.15146 RDF (Synopsys) 1.025137 RDDLERLWR OTF ITC PSG

22. 15/09/2015 22 15/09/2015 22 T2.2.3 Overview [V]σV T [mV] RDD (Glasgow) 1.02141 RDD (Numonyx) 1.15146 RDD+Rounded (Numonyx) 1.19161 Flat AA &FG Rounded AA & FG [V]σV T [mV] Calc. σV T [mV] Uniform 1.04-- All Sources 1.32169166.3

23. T2.2 action items Task 2.2: Device simulation –D2.2.4 (M24): « Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET)”  AI (STF2, Nov 2010): to provide TCAD decks. 5-way NDA between UNGL- UNET-SNPS-POLI-ST applies. –D2.2.5 (M27): « TCAD based assessment of PV effects of potential 22nm device architectures (UNGL)” => AI (WP leader, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011. –D2.2.6 (M36): « Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET). Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD. Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2)” => AI(T2.2 Leader): Contact SNPS if they intend to contribute to toolbox Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 23

24. MODERN General Meeting Task 2.3 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010 15/09/2015 24

25. Project Review Meeting Crolles, June 22, 2009 15/09/2015 25 Project Review Meeting Crolles, June 22, 2009 15/09/2015 25 Electrical Characterization: T2.3 Deliverables RefDeliverable/ ContributorsDue date D2.3.1Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (STF2, IMEP, UNET, NXP) Experimental characterization of Non-Volatile- Memory devices in the presence of PV (NMX, UNET) Parametric mismatch fluctuation effects in 32 nm FinFETs, first PV results on 22nm FDSOI MOSFETS (LETI, NXP) M12 D2.3.2Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (ST-I) Report on 1/f noise dispersion behavior in 45nm bulk CMOS (NXP) M18 D2.3.3Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware (STF2, NXP, UNET, AMS) Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS (IMEP, NXP, LETI) M30 D2.3.4Report on high-level models, both analytical and graphical, for PV of Non-Volatile- Memory devices (NMX) Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS (NXP) M36 Task Leader: hans.tuinhout@nxp.com

26. 26 MODERN 1st Year Review June 30, 2010 26 MODERN 1st Year Review June 30, 2010 26 MODERN 1st Year Review June 22, 2010 Task T2.3 D2.3.1: Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (ST, IMEP, UNGL) W (µm)L (µm) 0.125 10.04 5 0.150.04 0.151 0.121 10.05 10.08 0.120.05 0.120.2 Example of 45nm Nmos with pocket implants: Conventional DOE and electrical characterization technique Geometry scaling on transistor area impacted by Lateral doping gradient Compact analytical model developed with 3 channel regions wi/wo pockets explains qualitative trend of Lscaling for VT mismatch UNGL 3D simulation (D2.2.2) in line with experiments

27. 27 MODERN 1st Year Review June 30, 2010 27 MODERN 1st Year Review June 30, 2010 27 MODERN 1st Year Review June 22, 2010 Task T2.3 D2.3.1: Experimental characterization of NVM devices (41nm, xGbits )in the presence of PV (NMX) Neutral device scaling: Local random variations for W,L, Oxide, Interpoly dielectric, RDD fluctuations (top) Local systematic: Cell to cell interference (bottom) After programming: Local random Local systematic VT Shift induced by neighbouring cells (top), or string series resistances (bottom)

28. 28 MODERN 1st Year Review June 30, 2010 28 MODERN 1st Year Review June 30, 2010 28 MODERN 1st Year Review June 22, 2010 Task T2.3 D2.3.1: First PV results on 22nm FDSOI MOSFETS (Leti, NXP) V T mismatch (@ 1V Vd) for FDSOI nFETs and pFETs. High-k/metal gate stack. STI isolation. T Si =6nm, L min =30nm, W min =80nm Record matching performance for FDSOI (top) VT matching not degraded by UTBOX vs Thick box substrates (bottom) V T mismatch for UT2B vs thick BOX MOSFETs. High-k/metal gate stack. STI isolation. T Si =8nm.

29. 29 MODERN 1st Year Review June 30, 2010 29 MODERN 1st Year Review June 30, 2010 29 MODERN 1st Year Review June 22, 2010 Task T2.3 D2.3.1: Parametric mismatch fluctuation effects in 32 nm SOI FinFETs (NXP, LETI) Mismatch signature analysis on FinFET population. W Fin =10 nm, L g =100 nm a: collection of 96 (V DS =1.2 V) transfer curves for transistor 1 (I D1 ) of each pair. b: ΔI D /I D vs. V GS for all pairs of the population (ΔI D /I D = 200 x (I D1 -I D2 )/(I D1 +I D2 ) ). c: mismatch signature: σ_ΔI D /I D (red triangles) and mismatch auto-correlation (black X’s) vs. V GS. Rseries VT GIDL a: Drain access resistance improvement from 700 to 280 Ωμm. θ vs. β slope corresponds to R SD. b: V T mismatch fluctuations vs. area. A ΔVT increases from 1.9 mVμm (solid line) to 2.4 mVμm (dashed line) with 10 18 channel doping Powerful Mismatch signature analysis concept demonstrated A ΔVT down to 2 mVμm range demonstrated

30. T2.3 action items Task 2.3: Characterization and simulation verification –D2.3.2 (M18)/D2.3.4 (M36): « 1/f noise dispersion” => AI (WP leader): Ask NXP about plan to develop compact model within Modern –D2.3.4: (M36) « Report on high-level models, both analytical and graphical, for PV of in Non-Volatile-Memory devices (NMX)”  AI change title: « Report on high-level models, both analytical and graphical, for PV of devices in Non-Volatile-Memory technologies (NMX)” Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 30

31. MODERN General Meeting Task 2.4 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010 15/09/2015 31

32. Reliability: T2.4 Deliverables RefDeliverable/ ContributorsDue date D2.4.1Specification of considered degradation effects, modeling approaches and device parameters (UNGL, TUW) M6 (Done) D2.4.2Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA) M24 D2.4.3Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA) M33 Task Leader: Jong-mun.park@austriamicrosystems.com MODERN General Meetings Catania, Nov. 9 & 10, 2010 32

33. WP2/ Task 2.4 contributions Effects -> Technologies HCINBTITDDBRTN/Trapping/ De-trapping SBD/BD HV mosAMS TUW AMS TUW 65nm cmosUNCA (NXP) 45nm cmosUNGL UNCA (NXP) UNGL NVMUNET (NMX) Thin SiIMEP MODERN General Meetings Catania, Nov. 9 & 10, 2010 33 AI(all, end 2010): WP2 and per Task work matrix completion

34. T2.4 Review Summary Activity done so far, with highlights on technical results, and dissemination - D2.4.1 deliverable: done. - NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations. - Initial physics-based analytical model for NBTI to implement in circuit simulator. - Time dependent modeling of degradation for NBTI & HC. Plan for D2.4.2 deliverable (M24): - TCAD reliability simulations focused on HV-CMOS. - Hot-Carrier lifetime model for HV-CMOS by modified Hu-model. - Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node. Plan for D2.4.3 deliverable (M33): - Statistical compact Models will be extracted at different levels of NBTI and PBTI. - Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time. - Analytical NBTI and HC model developments for LV- & HV-CMOS. MODERN General Meetings Catania, Nov. 9 & 10, 2010 34

35. 35 NBTI & Hot-Carrier Activities (1) Extraction of capture/emission time maps –Compact modeling using RC circuits MODERN General Meetings Catania, Nov. 9 & 10, 2010

36. SE-mechanism: ME-mechanism: I dlin degradation represented by the compact model 36 MODERN General Meetings Catania, Nov. 9 & 10, 2010 NBTI & Hot-Carrier Activities(2)

37. MODERN General Meetings Catania, Nov. 9 & 10, 2010 37 Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node

38. Lifetime Models for High-Voltage NMOS Modified Model of Hu: blue data points: -40°C red data points: +25°C V d : 35V, 40V, 45V, 50V, 55V MODERN General Meetings Catania, Nov. 9 & 10, 2010 38

39. WP2 action items Task 2.4: Statistical Reliability –D2.4.2 (M24): « Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA)” => AI (UNCA, working with NXP): addition of sub-Vt slope to Vt figure for HCI effects –D2.4.3 (M33) « Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA)”  AI (AMS, TUW): Implementation of process variations in NBTI/HCI degradation compact models for HV devices remains challenging task (physics complexity); nevertheless achievable with some approximations to physics  AI (UNGL): UNGL to clarify contents of contribution to NBTI/HCI compact models Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 39

40. MODERN General Meeting Task 2.5 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010 15/09/2015 40

41. Project Review Meeting Catania, Nov. 9-10, 2010 15/09/2015 41 15/09/2015 41 Compact Modeling: T2.5 Deliverables RefDeliverable/ ContributorsDue date D2.5.1PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2), and Non-Volatile-Memory technologies (NMX, UNET), and Discrete Power Device,SiC, GaN/AlGaN technologies (ST-I). State-of-the-art based statistical models, based on hardware and/or TCAD M18 DONE D2.5.2Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS) M30 D2.5.3PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2) Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET) M33 Task Leader: paolo.pavan@unimore.it

42. 42 Local Statistical Channel dopants Poly Si granularity Line edge roughness Across chip Global Process Die to die Wafer to wafer Variations in statistical models: sources Local Systematic ( Layout dependent ) H.Tsuno, Sony, VLSI 2007 Source: A.Asenov

43. 43 UNGL Deliverable 2.5.1 Extraction of accurate uniform compact models, DC and AC 43 MODERN General Meetings Catania, Nov. 9 & 10, 2010 NMOS I D V D NMOS with substrate bias Capacitance fit at V D =0V Capacitance fit at V D =1.1V

44. 44 UNGL Deliverable 2.5.1 Selection of optimal statistical parameter set and statistical compact model extraction Preservation of parameter correlations 44 MODERN General Meetings Catania, Nov. 9 & 10, 2010 Distribution of fitted error for different parameter sets NMOS and PMOS parameter correlations

45. Statistical Models for Circuit Simulation 45 Circuit environment VDD, T, … Settings for Variations: Corners/ MC/ DOEs Design inputs Distributions Corners Yield Design Analysis Complete simulation file Core Compact model Simulation engine Elementary Circuit Responses Statistical models: MC, Corners Variations: Global Local Layout Proximity / Middle end Parasitics Spice model Nominal Corners construction Netlist extracted from Layout

46. T2.5 action items Task 2.5: compact modeling –D2.5.2 (M30): » Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)”  AI (STF2, Dec 2010): To clarify if D2.5.3 contribution (45nm Analog) effectively transforms into D2.5.2 contribution (32nm Digital) –D2.5.3 (M33): « PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2). Modeling of additional variability sources of 3- dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET)” => AI(WP leader, same as AI as D2.2.5, Nov 2010): to contact LETI, cc UNGL on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011. Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 46

47. Contents WP2 introduction Task 2.1 to 2.5 summary Matrix, Gantt chart, relation with other Wps Action points from meeting Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 47

48. 48 WP2 meeting Domain overview per task and partner MODERN General Meetings Catania, Nov. 9 & 10, 2010 Technologi es Process simulation Device simulation Electrical Charact. ReliabilityCompact Modeling Task2.12.22.32.42.5 HVMOSAMS TUW Planar CMOS65nmUNCA 45nmUNGL POLI SNPS (STF2) IMEP STF2UNGLUNGL POLI STF2 NXP 32nmUNGL POLI (STF2) IMEP STF2UNGL NVM41nmUNET NMX SNPS UNET NMXUNET (NMX)UNET NMX FDSOIIMEP (STF2)LETI IMEPLETI Finfets, MUG, GAA STF2NXPIMEP SiC Power MOS STI AlGaN-GaN HEMT STI PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1). Significant communalities of technology targets, except different ones for Process and Device simulation. (not funded)

49. WP2/ Task 2.4 contributions Effects -> Technologies HCINBTITDDBRTN/Trapping/ De-trapping SBD/BD HV mosAMS TUW AMS TUW 65nm cmosUNCA (NXP) 45nm cmosUNGL UNCA (NXP) UNGL NVMUNET (NMX) Thin SiIMEP MODERN General Meetings Catania, Nov. 9 & 10, 2010 49 AI(all, end 2010): WP2 and per Task work matrix completion

50. Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 50 WP2 meeting: Gantt chart AI(all): requires completion (links with other WPs), and review by email within 2 months

51. WP2 action items WP2 –Need to Complete WP2 matrix + 1 matrix per task –Need to Complete Gantt chart  AI (all, Jan 2010).  WP leader to send email for feedback collection Nov 2010.  WP2 members to feedback to Task Leaders, who will compile and update per task. Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 51

52. Contents WP2 introduction Task 2.1 to 2.5 summary Matrix, Gantt chart, relation with other Wps Backup: List of Action points from meeting Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 52

53. WP2 action items WP2 –Need to Complete WP2 matrix + 1 matrix per task –Need to Complete Gantt chart => AI (all, Jan 2010). WP leader to send email for feedback collection Nov 2010. WP2 members to feedback to Task Leaders, who will compile and update per task. Task 2.1: Process simulation –D2.1.2 (M27): « Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) »  AI (STI, AMS, M27): HVMOS and AsGaN-SiC device sensitivity analysis to Process variations to be validated on HW data available from D2.3.2 Task 2.2: Device simulation –D2.2.4 (M24): « Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET)”  AI (STF2, Nov 2010): to provide TCAD decks. 5-way NDA between UNGL-UNET-SNPS- POLI-ST applies. Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 53

54. WP2 action items Task 2.2 –D2.2.5 (M27): « TCAD based assessment of PV effects of potential 22nm device architectures (UNGL)” => AI (WP leader, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011. –D2.2.6 (M36): « Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET). Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD. Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2)” => AI(T2.2 Leader): Contact SNPS if they intend to contribute to toolbox Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 54

55. WP2 action items Task 2.3: Characterization and simulation verification –D2.3.2 (M18)/D2.3.4 (M36): « 1/f noise dispersion” => AI (WP leader): Ask NXP about plan to develop compact model within Modern –D2.3.4: (M36) « Report on high-level models, both analytical and graphical, for PV of in Non-Volatile-Memory devices (NMX)”  AI change title: « Report on high-level models, both analytical and graphical, for PV of devices in Non-Volatile-Memory technologies (NMX)” Task 2.4: Reliability –D2.4.2 (M24): « Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA)” => AI (UNCA, working with NXP): addition of sub-Vt slope to Vt figure for HCI effects –D2.4.3 (M33) « Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA)”  AI (AMS, TUW): Implementation of process variations in NBTI/HCI degradation compact models for HV devices (Challenging, nevertheless achievable with some approximations to physics)  AI (UNGL): UNGL to clarify contribution to NBTI/HCI compact models Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 55

56. WP2 action items Task 2.5: compact modeling –D2.5.2 (M30): » Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)”  AI (STF2): Clarifies if D2.5.3 contribution (45nm Analog) transforms into D2.5.2 contribution (32nm Digital) –D2.5.3 (M33): « PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2). Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET)” => AI(WP leader, same as AI as D2.2.5, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011. Project Review Meeting Catania, Nov 09-10, 2010 15/09/2015 56