MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31) WP1: Giuliana GangemiWP2:

MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31) WP1: Giuliana GangemiWP2: André Juge WP3: Wilmar HeuvelmanWP4: Fabio Campi WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: March 1 st, 2010

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Agenda (1) General information (Jan) –Objectives –Consortium –Relationship between workpackages –Gantt Chart –Resources planned and used –Overview of deliverables and milestones status –Cooperation, dissemination and exploitation –Project management: progress, funding problems and amendments –Other issues, Q&A For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Fabio) –Relationship between workpackages –Progress, highlights and lowlights –Matrices showing ‘Domain and Technology Overview per Task and Partner’ –Link with other WPs and Tasks –Technical status and achievements of deliverables (incl. changes) –Cooperation –Dissemination (publications, patents), exploitation –Other issues, Q&A 2

CONFIDENTIAL Agenda (2) For WP5 (Loris) –Relationship between workpackages –Progress, highlights and lowlights –Technical status and achievements of deliverables (incl. changes) –Structuring of demonstrators: goals and objectives –Link with other WPs and Tasks –Cooperation –Dissemination (publications, patents), exploitation –Other issues, Q&A MODERN 2010 Review March 1st, 2011 3

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Objectives The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. Specifically, the main goals of the project are:  Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures.  Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. oReliability, noise, EMC/EMI. oTiming, power and yield.  Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.  Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys) 4

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Consortium The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. 5

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Relationship between workpackages 6

CONFIDENTIAL Gantt Chart (1) MODERN 2010 Review March 1st, 2011 7

CONFIDENTIAL Gantt Chart (2) MODERN 2010 Review March 1st, 2011 8

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Resources planned and used 9

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Overview of deliverables and milestones status (1) Deliverables 10

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Overview of deliverables and milestones status (2) Milestones Conclusion: All Deliverables and Milestones due before 31-12-2010 (M22) are ready M24 Deliverables and Milestones are on schedule 11

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Website Public section Restricted section 12

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Cooperation, dissemination and exploitation A Workshop at DATE 2010 with the theme ‘The Fruits of Variability Research in Europe’ was organized. This workshop was a co-operation of the UK EPSRC project, FP7 STREP project REALITY and MODERN VARI Workshop, 2010 May 26-27, Montpellier, France Contribution to the Workshop on Simulation and Characterisation of Statistical CMOS Variability and Reliability was presented, Sept. 9 th 2010, Bologna, Italy MODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2010 in Madrid, Spain Large number of publications Main meetings: –General meetings in Catania (Nov. 9&10, 2010) attended by 30+ persons present and 10+ called in Due to the travel restrictions that many companies/institutes still face most of the interaction between partners is by phone and email 13

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Project management: progress, funding problems and amendments Progress: All planned deliverables ready Most uncertainties in countries causing funding and (national) administrative issues e.g. Italy, Swiss, Spain and Austria are resolved Amendments: 1.The change of project coordinator from ST to NXP and ST-Crolles being replaced by ST-Grenoble 2.The removal of some inconsistencies between some deliverables 3.The subcontracting of work by Glasgow to GSS Ltd. 4.CSEM withdraws due to lack of national funding as of 29-06-2010 5.To account for the leaving of some NXP employees and a related change in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed 6.To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed 7.Coming: partner #6 Infineon Technologies Austria AG is included in the transaction between Infineon and Intel 14

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Other issues Q&A Italy ? Payment to Spanish partner ? 15

CONFIDENTIAL WP1 agenda Introduction Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 Link with other WPs and Tasks Cooperation Other issues, Q&A MODERN 2010 Review March 1st, 2011 16

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 Introduction: Progress, highlights and lowlights 1. Clearly define the issues related to nano-electronic technologies that will be tackled in the MODERN project (e.g.,sensitivity of performances, power, yield, deficiencies of existing design techniques, etc). 2. Set the target technologies for which the above listed problems will be faced. 3. Define the specifications of the prototype tools, methods and flows that will come up as solutions of the previously listed problems. 4. Define the requirements of the integration work needed to embed the new tools into the existing design frameworks provided by the EDA partners within the flows in use at ST, NMX, IFX,THL, AMS and NXP. 5. Define up front all activities of all WPs of MODERN exception made of the management. HIGHLIGHT : Activities recovered past delay D1.3 released OCT 2010 M1.1Problem definition and Tests M1.2 Integraton specs M1.4 user guides PERIOD UNDER REVIEW 17

CONFIDENTIAL Matrices showing ‘Domain and Technology Overview per Task and Partner’ D1.3 WP2 device Digital, NVM, and AMS WP3 block digital, AMS, RF, NVM WP4 system NXPXX AMSX STXXX IFXX NMXXXX THLXX MODERN 2010 Review March 1st, 2011 18

CONFIDENTIAL Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011 WP2WP3WP4 NXP Matching and 1/f-noise results will be integrated in process blocks and PDK’s. The data we collect, analyze, and model are used by the FT/DKD group in NXP-Nijmegen to construct the appropriate process blocks for circuit simulations. Equally important is the fact that we use the results measured on advanced technologies to assess where, when and how future models and process blocks should be modified, refined or expanded. For this we also use the data from other partners  Substrate noise: implementation through guidelines (documentation) and design reviews  Model Order Reduction: implementation through guidelines, training and supplying a toolbox (plug & play)  EM simulation methodology: implementation through guidelines (documentation) Not involved AMS  After survey of results T1.2 in WP5, tools and environment must be optimized for the final implementation in the AMS characterization and modelling flow.  The main outcome of the T2.2 task, aging modelling of HV transistors including PV will be implemented in the AMS simulation environment. At the end of the day the AMS HitKIT will extended with PV lifetime simulators for low voltage and high voltage transistors. As within the Modern project only a few and HV transistors are used as demonstrators for this approach. All other devices in the AMS HV CMOS technologies will be carried out with PV aging models in the next future.  Matching parameters and also additional analog parameters will be directly implemented in the AMS HiTKIT based on the developments performed in MODERN. Not involved 19

CONFIDENTIAL Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011 WP2WP3WP4 ST PV aware spice Spice Models will be implemented in the ST-I simulation environment. The models are “plug and play” they do not need any integration work T3.1 and T3.2 At the end of the project we shall update ST digital design flow, introducing additional degrees of freedom to maximizing delay sensitivity to FBB keeping the overhead leakage power and area cost as lower as possible while the models created for the Analog IC flow are "plug and play" i.e. do not require integrationwork  All the methodologies developed in T4.2 as part of this task were designed keeping as a strict constraint the easy interoperability with standard RTL-to-GDSII design tools. The proposed methodologies were conceived, designed and verified with the specific aim of being "pluggable" in the existing design flow as an additional, stand-alone extra step that could enhance final performance results without altering the flow in itself.  In T4.4 o Regarding the metal programmable flow the RTL generated by the flow must be compliant with synthesis tools utilized in ST (e.g. Synopsys design compiler). o Regarding the metal programmable flow the RTL generated by the flow must be compliant with synthesis tools utilized in ST (e.g. Synopsys design compiler) o The “skeleton” layout and schematic containing the not- programmed datapath tiles will be realized utilizing a standard design flow. The customization of the skeleton layout and schematic will be automatically performed utilizing a skill (Cadence) script which generates a VIA4 OPUS layer of the specific accelerator implemented starting from the bitstream output of the Griffy front end flow. The skeleton layout and schematic will be further imported in Cadence OPUS and all libraries and views will be exported. 20

CONFIDENTIAL Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011 WP2WP3WP4 IFX Not involved  Aging model parameters for analog reliability simulator Virtuoso® RelXpert have been extracted and will be made available as add-on to standard PDKs in design/verification flow.  Results from basic assessment of aging/reliability issues and aging induced PV in key AMS&RF building blocks will be compiled into a comprehensive documentation & catalogue (“impact matrix”) that gives circuit designers guidelines in terms of expected aging impact and strategies how to avoid, minimize or compensate effects accordingly. This documentation will be part of standard verification plans.  In a similar way the developed monitor & control circuit IP portfolio (to enable aging/reliability insensitive analog, mixed-signal and & RF circuits) will be included in the documentation. In addition prototype designs will be made available to the circuit designers Not involved NMX s oftware tools both internal and commercial have been and/or are going to be improved with respect to PV in terms of models, efficiency, usability (allowing to avoid workarounds in handling discrete dopants/traps whitin ‘concentration’ based tools).This does not require any integration work just upgrade the version of the tool The simplified and time saving methodology available in the company will be cross-checked against more complete and computationally heavy approaches available in academia to verify (or, if necessary, improve) the coverage of the industrial flow. This work is done internally without partners, therefore does not require an integration plan. 21

CONFIDENTIAL Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011 WP2WP3WP4 THL Not involved modify the toolchain, validate the architecture principles with a SystemC simulator and develop a usecase 22

CONFIDENTIAL Link with other WPs and Tasks MODERN 2010 Review March 1st, 2011 23

CONFIDENTIAL Collaborations WP leader: ST-I Strong dependence on partners: NMX, NXP,THL,IFX,AMS,ST-I, ST-F Collaboration with partners: NMX, NXP,THL,IFX,AMS,ST-I,SNPS,ST-F, Telephone conferences with: NMX,NXP,THL,IFX,AMS,ST-I,SNPS,ST-F according requirements of deliverables ALL SEPT – OCT 2010. With WP Leaders weekly since the month of December MODERN 2010 Review March 1st, 2011 24

CONFIDENTIAL WP2 agenda Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ Link with other WPs and Tasks Technical status and achievements of deliverables (incl. changes): D2.1.1, D2.2.3, D2.3.2 and D2.5.1 Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A 25 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP2 Objectives Provide a chain of TCAD simulations tools which enable simulation of the impact of process variations and reliability on device level, including compact models and mixed mode device/circuit simulation Assess the impact of process and device variations for relevant technologies, mainstream planar bulk CMOS down to 45/32nm, new device architectures on bulk & on SOI suitable for 22nm, NVM technologies, and non-silicon technologies Compare simulation results with hardware and calibrate them on hardware to verify PV methodology and to foster physical understanding of major sources of PV in above technologies Key-figures: 5 Tasks/18 deliverables (reports): –Process (2) & device (6) simulation –Electrical characterization (4) & Reliability(3) –Compact modeling (3) –Covering both Tools/Methodology improvements and Application results Wide spectrum of technologies & devices applications –45nm: planar Mosfet –32nm: planar Mosfet, FinFet –22nm: FD SOI Mosfet –State-of-art NVM –Discrete Power Device, SiC, GaN/AlGaN –HV CMOS 26 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 27 WP2 Task Structure and Contributors WP2Process/Device to Compact ModelingContributors T2.1PV aware process simulationST-I, AMS, TUW T2.2PV aware device simulation UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS T2.3 Electrical characterization of PV, software (TCAD) / hardware comparison & calibration NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I T2.4 Correlation between PV and reliability, reliability modeling AMS, IMEP, UNET, TUW, UNCA, UNGL T2.5PV aware compact modeling UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNG MODERN 2010 Review March 1st, 2011 27

CONFIDENTIAL WP2 Domain and Technology overview per task and partner Technologi es Process simulation Device simulation Electrical Charact. ReliabilityCompact Modeling Task2.12.22.32.42.5 Planar CMOS65nmUNCA 45nmUNGL POLI SNPS (STF2) IMEP STF2UNGLUNGL POLI STF2 NXP 32nmUNGL POLI (STF2) IMEP STF2UNGL STF2 NVM41nmUNET NMX SNPS UNET NMXUNET (NMX)UNET NMX FDSOIIMEP (STF2)LETI IMEPLETI Finfets, MUG, GAA STF2NXPIMEP HVMOSAMS TUW SiC, Power MOS STI AlGaN-GaN HEMT STI PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1). Significant communalities of technology targets, except different ones for Process and Device simulation. (not funded) 28 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP2: Links with other WPs and Tasks 29 MODERN 2010 Review March 1st, 2011 WP2 T2.4 T2.3 WP4 T4.1 T4.2 T5.2T5.3 WP5 T5.1 WP3 T3.1 T3.2 T3.3 T3.4 LETI IFX T4.4 T2.5 T2.1 T2.2

CONFIDENTIAL WP2 Progress, Highlights and Lowlights Progress: –Project on track. 4 deliverables completed in 2010: D2.1.1, D2.2.3, D2.3.2 and D2.5.1 –Overall 8 deliverables over 18 completed so far March-Dec 2010 period highlights: –Process variations: TCAD method for process compact modeling (PCM) demonstrated in HVMOS and Power MOS technologies (STI, AMS, TUW). –Device simulation: analysis of dominant variability sources in state of-the-art Non-Volatile-Memory technologies (UNET, UNGL, NMX, SNPS). Consistency of variability estimates over different tools and methods for NVM devices (UNET, NMX, UNGL, SNPS) –Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (ST-I) –Characterization of 1/f noise dispersion behavior in 45nm bulk CMOS (NXP) –PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2), and Non-Volatile-Memory technologies (NMX, UNET) Lowlights: –2010: D2.3.2 delayed M18->M21 –2011: 4 months delay expected for coming D2.2.4 (consistent 32nm core Cmos data required for D224, D233, and D253) 30 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 31 Task 2.1 PV aware Process simulation RefDeliverable/ ContributorsDue date D2.1.1First process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) M15 Done D2.1.2Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) M27 In progress Task Leader: valeria.cinnera@st.com MODERN 2010 Review March 1st, 2011 Goal: To perform process simulation including treatment of PV. Application to discrete power devices, SiC, AlGaN/GaN (ST-I) and HV-CMOS technologies (AMS). 31

CONFIDENTIAL 32 MODERN 2010 Review March 1st, 2011 32 Partners: ST-I, AMS, TUW Progress: TCAD method for process compact modeling (PCM) demonstrated in Power MOS (STI) and HVMOS technology (AMS, TUW). Aim is to propagate Fab equipment tolerance (1) to Process variations and (2) to Device level, and to determine Device performances variations in terms of sensitivities, distributions,and yield estimates TOOL is under construction; a β-release has been created Done for Silicon Power Mos (STI), HV Mosfets (AMS) Running for AlGaN/GaN Hemt and SiC diode (STI). TOOL links with : Sentaurus Process (all), Sentaurus Device (STI), Minimos (TUW), PCM studio(all) Next activities: In the final report D2.1.2 (M27) will be also addressed: - an interface between the semiconductor FAB equipment and the process simulation environment, to enable analysis of variations, and yield estimates - an interface between commercial process simulator and Minimos-NT (a two-dimensional device simulator from TUW) - the activity done on a Silicon Power MOS will be extended to compound materials (STI). T2.1 Progress

CONFIDENTIAL T2.1 PV aware process simulation (ST-I) High Level factory Process recipes Specific process conditions Mask Layout Process flow Virtual device TCAD Experiments Process Compact model derived from TCAD PCM FAB1 FAB2 Technology transferred to FAB2 using PCM 33 MODERN 2010 Review March 1st, 2011 33

CONFIDENTIAL PCM approach (STI) Parameter screening to identify the process parameters that have an important impact on target electrical parameters. Parameterized simulation setup (DOE) generating several simulation runs. Device simulations of breakdown and I-V characteristic for each experiment. Extraction of RSM model of device characteristics as function of process parameters using PCM Studio. D OE EHD5 SEMICELL SENTAURUS WORKBENCH PCM STUDIO PCM Synopsys platform: Sentaurus and PCM Studio Simulation of Power-Mos semi cell with the nominal values of the process input parameters 34 MODERN 2010 Review March 1st, 2011 34

CONFIDENTIAL T2.1 PV aware process simulation (AMS – TUW) Process Flow Process Parameters Sentaurus Work Bench Minimos Parameter Extraction Correlation Interface between commercial Synopsys Process Simulator and Minimos Device Simulator 35 MODERN 2010 Review March 1st, 2011 35

CONFIDENTIAL T2.2 PV aware Device Simulation RefDeliverable/ ContributorsDue date D2.2.1Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools (UNGL) M6 Done D2.2.2Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies, and Discrete Power Device,SiC, GaN/AlGaN technologies. Prototype implementation of the treatment of individual dopants and traps in the device modeling tools (UNGL, UNET, NXP, ST-I, SNPS) M12 Done D2.2.3Device simulation analysis of dominant variability sources in state of-the-art Non- Volatile-Memory technologies (UNET, UNGL, NMX, SNPS) M18 Done D2.2.4Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET). Efficient compact model extraction procedures for modeling process variations and device fluctuations (NXP, UNET, POLI) M24 In progress Request for delay M28 D2.2.5Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations (UNET) TCAD based assessment of PV effects of potential 22nm device architectures (UNGL) M27 D2.2.6Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET) Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2) M36 Task Leader: a.asenov@elec.gla.ac.uk 36 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 37 Partners: UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS Goal: The focus is on activities: to include variability in device simulation tools to illustrate the tool capabilities in respect of progressively scaled CMOS devices and to validate the simulation capabilities in respect of variability measurements of real devices Progress (achieved): D2.2.1 (M6): -A comprehensive review of the necessity for variability TCAD simulation. -Review of current industrial practices based on a comprehensive survey. -Prioritisation D2.2.2 (M12) -Study of 45nm CMOS -Stress effects on mobility in SOI and FinFETs -Development of Sentaurus and GARAND to include Variability. D2.2.3 (M18): next slides -Comprehensive study of Variability in a 32nm NVM Floating Gate Flash Cell -Development and comparison of simulators developed by Partners T2.2 Progress MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T2.3.3 NVM Template Structure Analyse the dominant variability sources in state of the art NVM technologies. NVM cell designed with a 32nm Half Pitch, TCAD supplied by Numonyx. 32nm channel length, with an area of 64x64nm. Indicative of 32nm technology but does not represent actual device or process. Used to investigate the impact of statistical variability on NVM. 38 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T2.2.3: NVM Variability Sources RDDLERLWROTFPSGITC [V]σV T [mV] RDD (Glasgow) 1.02141 RDD (Numonyx) 1.15146 RDF (Synopsys) 1.025137 39 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T2.2.3: NVM Variability Sources [V]σV T [mV] RDD 1.02141 LER 1.0448 OTF 1.0414 LWR 1.0426 PSG 1.2511 Traps 1.1867 40 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T2.2.3: NVM Rounded Gate [V]σV T [mV] RDD (Glasgow) 1.02141 RDD (Numonyx) 1.15146 RDD+Rounded (Numonyx) 1.19161 Flat AA &FG Rounded AA & FG 41 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 42 MODERN 2010 Review March 1st, 2011 ImplementationReleaseApplication Geometrical noise analysis 2010.03Applied to 45nm (ST Crolles) and 32nm devices (reference device), planned to be applied to NVM and to FinFET devices  done Random dopant fluctuation Implemented before project start Applied to 45nm (ST Crolles) and 32nm devices (reference device), planned to be applied to NVM and to FinFET devices  done Single traps2010.03Application to NVM and FinFet  ongoing work Randomization of traps 2010.03Application to NVM and FinFet  ongoing work Single dopands2010.12Application to NVM and FinFet  ongoing work Extension of geometrical noise analysis to 3D 2010.12Application to NVM and to FinFET devices  done Deterministic fluctuations 2010.12Planned to be applied to 45nm and 32nm bulk as well as to NVM and non-planar multi-gate devices (Finfet etc.)  to start Degradation of mobility by traps 2010.03, Improvements tentatively planned for 2010.12 Planned to be applied to 45nm and 32nm devices from ST Crolles and to FinFET devices Implementations in Sentaurus Device in the releases 2010.03 and 2010.12 with corresponding applications T2.2 3 simulation tools enhancements (example)

CONFIDENTIAL 43 MODERN 2010 Review March 1st, 2011 43 Partners: UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS Next activities: D2.2.4 (M24->M28) “Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET). Efficient compact model extraction procedures for modeling process variations and device fluctuations (NXP, UNET, POLI)” Some contributions in progress: UNGL Comprehensive simulation of variability in 32nm devices Statistical Compact Model extraction based on above Methodology has been created in D2.2.2 and D2.2.3 for large scale variability simulation Methodology for compact model extraction has been worked out in D2.5.1 - IMEP - Variability studies using 3D full quantum NEGF simulations of SiNW with the impact of surface roughness and discrete trap charge in gate all around dielectric - Semi-analytical modelling of drain current variability in C32 including dopant induced correlated mobility fluctuations - Influence of pockets in C32 using semi-analytical random dopant model - T2.2 PV aware Device Simulation: next activities

CONFIDENTIAL T2.3 Electrical characterization RefDeliverable/ ContributorsDue date D2.3.1Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (STF2, IMEP, UNET, NXP) Experimental characterization of Non-Volatile- Memory devices in the presence of PV (NMX, UNET) Parametric mismatch fluctuation effects in 32 nm FinFETs, first PV results on 22nm FDSOI MOSFETS (LETI, NXP) M12 Done D2.3.2Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (ST-I) Report on 1/f noise dispersion behavior in 45nm bulk CMOS (NXP) M18 Done D2.3.3Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware (STF2, NXP, UNET, AMS) Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS (IMEP, NXP, LETI) M30 In progress D2.3.4Report on high-level models, both analytical and graphical, for PV of Non-Volatile- Memory devices (NMX) Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS (NXP) M36 Task Leader: hans.tuinhout@nxp.com 44 MODERN 2010 Review March 1st, 2011 Goal is “Electrical characterization of PV, software (TCAD) / hardware comparison & calibration”

CONFIDENTIAL 45 MODERN 2010 Review March 1st, 2011 45 Partners: NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I, UNGL Progress: extension of Mismatch characterization to non Silicon technologies D2.3.2 (ST-I, NXP, due M18, see next slides): “Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices. Report on 1/f noise dispersion behavior in 45nm bulk CMOS” Next activities: D2.3.3 (STF2, NXP, UNET, AMS, LETI, due M30) « Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS” D2.3.4 (NMX, NXP, due M36) « Report on high-level models, both analytical and graphical, for PV of Non-Volatile-Memory devices. Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS” Task 2.3 Progress

CONFIDENTIAL 46 MODERN 2010 Review March 1st, 2011 WP2 D2.3.2 : Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (STI) Process variation impact on SIC diode (left) and AlGaN/GaN HEMT (right) Above HW data support TCAD validation in T2.1 Si(111) 500um AlN 0.18um AlGaN 0.4um GaN 1um AlGaN 0.04um

CONFIDENTIAL 47 MODERN 2010 Review March 1st, 2011 WP2 D2.3.2 : 1/f noise dispersion characterization of 45 nm bulk CMOS (NXP) Id noise current spectra (1Wafer, 65dies): Over 2 orders of magnitude Comparable noise dispersions in 65nm/45nm Area Scaling of LF Noise dispersion preserved from 180nm to 45nm LF noise Compact models from earlier nodes apply to 45nm

CONFIDENTIAL T2.4: Correlation between PV and reliability, reliability modelling RefDeliverable/ ContributorsDue date D2.4.1Specification of considered degradation effects, modeling approaches and device parameters (UNGL, TUW) M6 Done D2.4.2Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA) M24 In progress D2.4.3Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA) M33 Task Leader: Jong-mun.park@austriamicrosystems.com 48 MODERN 2010 Review March 1st, 2011 Goal: To develop and validate different level of models and tools for transistor level reliability that correlate reliability to PV and can be used at higher levels of the design process (AMS, IMEP, UNET, TUW, UNCA, UNGL)

CONFIDENTIAL 49 Partners: AMS, IMEP, UNET, TUW, UNCA, UNGL Activity done so far - D2.4.1 “Specification of considered degradation effects, modelling approaches and device parameters”. - NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations. - Initial physics-based analytical model for NBTI to implement in circuit simulator. - Time dependent modeling of degradation for NBTI & HC. Plan for D2.4.2 deliverable (M24): - TCAD reliability simulations focused on HV-CMOS. - Hot-Carrier lifetime model for HV-CMOS by modified Hu-model. - Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node. Plan for D2.4.3 deliverable (M33): - Statistical compact Models will be extracted at different levels of NBTI and PBTI. - Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time. - Analytical NBTI and HC model developments for LV- & HV-CMOS. Remains challenging task for HV-MOS devices, because of coupling between degradation effects and others (self-heating,…). WP2 Task 2.4 Progress MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP2/ Task 2.4 contributions Effects -> Technologies HCINBTITDDBRTN/Trapping/ De-trapping SBD/BD HV mosAMS TUW AMS TUW 65nm cmosUNCA (NXP) 45nm cmosUNGL UNCA (NXP) UNGL NVMUNET (NMX) Thin SiIMEP 50 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL NBTI & Hot-Carrier Activities (1) Extraction of capture/emission time maps –Compact modeling using RC circuits 51 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL SE-mechanism: ME-mechanism: I dlin degradation represented by the compact model NBTI & Hot-Carrier Activities(2) 52 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node 53 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Lifetime Models for High-Voltage NMOS Modified Model of Hu: blue data points: -40°C red data points: +25°C V d : 35V, 40V, 45V, 50V, 55V 54 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Compact Modeling: T2.5 Deliverables RefDeliverable/ ContributorsDue date D2.5.1PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2), and Non-Volatile-Memory technologies (NMX, UNET), and Discrete Power Device,SiC, GaN/AlGaN technologies (ST-I). State-of-the-art based statistical models, based on hardware and/or TCAD M18 Done D2.5.2Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS) M30 In progress D2.5.3PV-aware circuit-level models for 45nm analog 32nm CMOS technology (ST-F2) Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET) M33 Request for change (STF2) Task Leader: paolo.pavan@unimore.it 55 MODERN 2010 Review March 1st, 2011 Goal: focus of Task 2.5 “PV-aware Compact Modeling” is to implement PV and reliability effects in device compact models to be able to accurately describe the impact of variability on circuit operation (UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNGL.

CONFIDENTIAL D2.5.1 – M18 – delivered This deliverable describes several approaches to capturing the effects of process and, particularly, statistical variability in PSP compact models. PSP was adopted since it is more physically based and is becoming the new industry standard compact model. Uniform, statistical and width-dependent parameter extraction techniques were illustrated by UNGL, based on physical simulations carried out using the ‘atomistic’ simulator GARAND. An approach to capturing process, on-chip and random variations was developed by STF2 and the impact on circuits designed with 45 nm technology was illustrated. A Green’s function approach to capturing the effect of statistical doping fluctuations was outlined by POLI and validated using 2D TCAD simulations with Synopsys Sentaurus. 56 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Local Statistical Channel dopants Poly Si granularity Line edge roughness Across chip Global Process Die to die Wafer to wafer Variations in statistical models: sources Local Systematic ( Layout dependent ) H.Tsuno, Sony, VLSI 2007 Source: A.Asenov 57 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL UNGL Deliverable 2.5.1 Extraction of accurate uniform compact models, DC and AC NMOS I D V D NMOS with substrate bias Capacitance fit at V D =0V Capacitance fit at V D =1.1V 58 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL UNGL Deliverable 2.5.1 Selection of optimal statistical parameter set and statistical compact model extraction Preservation of parameter correlations Distribution of fitted error for different parameter sets NMOS and PMOS parameter correlations 59 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL TL CL BL TC TR CC CR BCBR Chip L Chip W Variations in statistical models: Across Chip (STF2) Variation normalized to CC position: Low range (+/-1%) Evidence of Ion_N Ion_P correlation Evidence of Frequency – Ion correlation 60 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Statistical Models for Circuit Simulation (STF2) Circuit environment VDD, T, … Settings for Variations: Corners/ MC/ DOEs Design inputs Distributions Corners Yield Design Analysis Complete simulation file Core Compact model Simulation engine Elementary Circuit Responses Statistical models: MC, Corners Variations: Global Local Layout Proximity / Middle end Parasitics Spice model Nominal Corners construction Netlist extracted from Layout 61 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Variations impact: RO example (STF2) Global Local Global+ Local W ref tdsat Global Local Global+ Local Inverter ring: Trise Global Local Global+ Local Inverter ring: Period σIdsatTrisePeriod Global111 Local110.16 All1.4 1.02  Variations impact :  Transistor: Local ~ Global  Inverter Rise time : Local ~ Global  Inverter Period: Local << Global  Circuit design needs:  Accurate compact statistical models  Accurate/efficient simulation methods 62 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL D2.5.2 activities in progress D2.5.2 (M30)“Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)” –Some partners already active (POLI, UNGL, UNET) –POLI will carry on PV aware compact modeling in conjunction with the activities carried out in T2.2 (on the basis of the sensitivity approach) extend to 32nm process –UNGL will create statistical compact model extraction strategies based on the comprehensive statistical simulation carried out in D2.2.4 investigate the sensitivity of compact model parameters for statistical compact model extraction investigate the accuracy of compact model parameters as a function of the statistical parameter set. apply PCA for width dependence of statistical parameter generation. –UNET has already completed and reported work on strain with NXP (paper at IEDM) will develop fast and efficient models for new physical effects in advanced MOSFETs (quasi ballistic transport) will work on Q.B.Transport with NXP Extremely efficient model for backscattering in nanoscale MOSFETs (elastic and inelastic) Fully calibrated and verified against Multi-Subband Monte Carlo simulations 63 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP2 cooperation (2010) T2.1: –STI, AMS, TUW on Process Variation aware Compact Modeling methodologies applied to HV MOS and Power Mos technologies T2.2: –UNGL, NMX, UNET, and SNPS on methodologies for simulating statistical variability in NVM technologies, and achieve comparable results with different tools and numerical methods T2.3: –IMEP and STF2 on mismatch characterization and compact modeling of pocket implants Mosfet devices in 45nm technology T2.4: –UNCA, UNGL and NXP on HCI degradation characterization and modeling in 45nm technologies –TUW and AMS on HCI and NBTI degradation characterization and compact modeling in HV MOS technologies T2.5: –UNGL, IMEP, STF2 on device simulation, electrical characterization, and compact modeling of statistical variations in 45nm, and in progress for 32nm technology –NMX, UNET-MI for PV aware circuit simulation model in NVM technologies –UNET and NXP on Q.B. transport WP2 review and coordination meeting, Catania, Nov 2010 64 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T2.2 publication list Journals V. Bonfiglio, G. Iannaccone, “An approach based on sensitivity analysis for the evaluation of process variability in nanoscale MOSFETs”, submitted to IEEE-TED, special issue on Variability A. R. Brown, V. Huard and A. Asenov, Statistical simulation of progressive NBTI degradation in a 45nm technology pMOSFET, IEEE Trans. on Electron Devices (in press) M. Faiz. Bukhori, S. Roy and A. Asenov, "Simulation of Statistical Aspects of Charge Trapping and Related Degradation in Bulk MOSFETs in the Presence of Random Discrete Dopants," IEEE Trans. Electron Dev. vol. 57, iss. 4, pp. 795–803, Apr. 2010. Workshops 2010 SISPAD workshop on Statistical Variability (UNGL) 2010 VARI workshop Montpellier Conferences Proceedings V. Bonfiglio, G. Iannaccone, “Evaluation of threshold voltage dispersion in 45nm CMOS technology with TCAD-based sensitivity analysis, Proc. 14 th International Workshop on Computational Electronics, IWCE 2010, Pisa, Italy 26-29 Oct 2010, pp. 101-104. V. Bonfiglio, G. Iannaccone, “Analytical and TCAD-supported approach to evaluate intrinsic process variability in nanoscale MOSFETs. A. Asenov, G. Roy, A. Ghetti, A. Benvenuti, A. Erlebach and A. Wettstein, “3D Simulation of Statistical Variability in Advanced Flash Memory Transistors“, presented at International Workshop on Non-Volatile Memory Modeling and Simulation (NVM2S) Agrate Brianza, 21/22-Sep-2010 65 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T2.3 publication list Journals P. Magnone, F. Crupi, A. Mercha, P. Andricciola, H. Tuinhout, R. J. P. Lander, “FinFET mismatch in subthreshold region: theory and experiments”, IEEE Transactions on Electron Devices, vol. 57, n. 11, pp. 2848-2856, 2010 C.M.Mezzomo, A.Bajeolet,A.Cathignol, E.Josse, G.Ghibaudo, « Modeling local electrical fluctuations in 45nm heavily pocket-implanted bulk MOSFET » SSE Journal, accepted June 2010 Workshops 2010 SISPAD workshop on Statistical Variability (UNGL) 2010 VARI workshop Montpellier 66 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T2.4 publication list 67 MODERN 2010 Review March 1st, 2011 Journals P. Magnone, F. Crupi, N. Wils, R. Jain, H. Tuinhout, P. Andricciola, G. Giusi, C. Fiegna,“Impact of Hot Carriers on nMOSFET variability in 45 nm and 65 nm CMOS Technologies”, to be submitted to IEEE Transactions on Electron Devices Conferences procedings A. Starkov, S.E. Tyaginov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Enichlmair, M. Karner, Ch. Kernstock, E. Seebacher, R. Minixhofer, H. Ceric, T. Grasser, “Analysis of Worst-Case Hot-Carrier Conditions for High Voltage Transistors Based on Full-Band Monte-Carlo Simulations,” in IEEE Intl. Symp. on the Physical and Failure Analysis of Integrated Circuits, 2010. Tyaginov, I.A. Starkov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Enichlmair, M. Karner, Ch. Kernstock, E. Seebacher, R. Minixhofer, H. Ceric, T. Grasser, “Hot-Carrier Degradation Modeling Using Full-Band Monte-Carlo Simulations,” in IEEE Intl. Symp. on the Physical and Failure Analysis of Integrated Circuits, 2010. Starkov, S. Tyaginov, H. Enichlmair, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Ceric, T. Grasser, “HC degradation model: interface state profile – simulations vs. experiment,” in Workshop on Dielectric Materials, 2010. Tyaginov, I.A. Starkov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Enichlmair, M. Karner, Ch. Kernstock, E. Seebacher, R. Minixhofer, H. Ceric, T. Grasser, “Interface states charges as a vital component for HC degradation modeling, European Symp. on Reliability of Electron Devices,” in Failure Physics and Analysis, 2010. Tyaginov, I.A. Starkov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Enichlmair, M. Karner, Ch. Kernstock, E.Seebacher, R. Minixhofer, H. Ceric, T. Grasser, “Interface Traps Density-Of-States as a Vital Component for Hot-Carrier Degradation Modeling”, Microelectronics Reliability, vol. 50, No. 9-11, pp. 1267-1272 (2011). Tyaginov, I.A. Starkov, H. Enichlmair, J.M. Park, Ch. Jungemann, and T. Grasser "Physics-Based Hot-Carrier Degradation Models“, ECS spring meeting 2011, invited paper, accepted.

CONFIDENTIAL T2.5 publication list JOURNAL PAPERS N. Serra and D. Esseni, “Mobility Enhancement in Strained n-FinFETs: Basic Insight and Stress Engineering”, IEEE Transactions on Electron Devices, Vol.57, NO.2, pp.482-490, February 2010 A. Paussa, F. Conzatti, D. Breda, R. Vermiglio, D. Esseni and P. Palestri, “Pseudospectral methods for the efficient simulation of quantization effects in nanoscale MOS transistors”, IEEE Transactions on Electron Devices, Vol. 57, NO. 12, pp. 3239-3249, December 2010 CONFERENCES J.-L.P.J. van der Steen, P. Palestri, D. Esseni and R.J.E. Hueting, “A New Model for the Backscatter Coefficient in Nanoscale MOSFETs”, European Solid-State Device Research Conference (ESSDERC), Siviglia (ES), 13-17 settembre 2010, pp. 234-237 A. Paussa, F. Conzatti, D. Breda, R. Vermiglio, D. Esseni, "Pseudo-Spectral Method for the Modelling of Quantization Effects in Nanoscale MOS Transistors", Proceedings International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Bologna (Italia), settembre 2010, pag. 299-302 Workshops SISPAD workshop on Statistical Variability (UNGL) 2010 VARI workshop Montpellier L. Masoero, F. Bonani, F. Cappelluti, G. Ghione, “Modeling the effect of position-dependent random dopant fluctuations on the process variability of submicron channel MOSFETs through charge-based compact models: a Green's function approach”, Proc. VARI, Montpellier, 2010 68 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP2 other issues, Q/A Request for changes: –D2.2.4 delayed from M24 to M28 –D2.5.3 STF2 contribution proposed to move from « 45nm analog » to « 32nm ». Consistency of data from D2.2.4, D2.3.3, D2.5.3 ensured. 69 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP3 agenda Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ Link with other WP’s and Tasks Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A 70 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 71 MODERN 2010 Review March 1st, 2011 WP3: Physical/circuit to RT-level Objective –PV-aware and PV-robust circuit design techniques and tools, enabling the design of reliable, low cost, low power, low EMI digital and AMS&RF products Tasks: 1.PV-aware circuit models 2.Methodologies, tools and flows for manufacturability, testability, reliability and yield 3.PV-aware design 4.Design for low noise and EMI/EMC Progress: –The activity is on track, and planned deliverables were delivered –milestones are on track –A number of scientific papers were published in 2010

CONFIDENTIAL WP3 Progress, highlights and lowlights All deliverables for 2010 delivered as planned (M12) Deliverables M24 are on track Highlights: –Very successful meeting with WP3 partners on Nov. 2010 in Catania –VARI 2010 conference organized by LIRMM Lowlights –Withdrawal of partner CSEM due to Swiss funding issues –Funding of Italian partners delayed 72 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP3 symbolic synergy 73 MODERN 2010 Review March 1st, 2011 T3.1 T3.2 T3.3 T3.4 Symbolic models Statistical models Etc. ABB techniques Random spice etc. M&C circuits PV-aware design Substrate noise Co- habitation EMI

CONFIDENTIAL WP3 Application overview per task and partner 74 MODERN 2010 Review March 1st, 2011 TasksCircuit ModelsMethods Tools&Flows PV aware Circuits EMI/EMC 3.13.23.33.4 Application DigitalNXP,STI,TUD,TUE, UNRM,LIRM UNBO,NXP,STI, UNCA, UNGL,UNRM POLI,LETI,UPCSTI,LIRM AMSSTI,UNRMNMX,STI,UNRMIFX,UPCNXP,STI RFNXPIFXNXP NVMNMX

CONFIDENTIAL WP3 Domain Overview per Task and Partner (tbd) 75 MODERN 2010 Review March 1st, 2011 T3.1T3.2T3.3T3.4 Digital circuit models TUD, LIRM, NXP, UNRM Statistical methods for digitalLIRM, TUE,TUD Analog circuit modelsSTI,UNRM Timing analysis TUD, TUE, NXP, LIRMM NXP AlgorithmsUNRM,STI Monte CarloUNCA Body BiasUNBO, STI Spice like simulationTUDUNGL, NMX Design methodologies UNBO,NMX,NXP, STI, UNCA, UNGL,UNRM Variability TUD,TUE,NXP, UNRM, STI,LIRM NMX,UNGLIFX EMC/EMINXP,STI Monitor & control for digitalPOLI,UPC,LETI,ST Monitor & control for analogIFX,UPC Regular cellsUPC Substrate NoiseNXP Chip-Package-PCB co-design NXP, ST Software and programming methodsNXP

CONFIDENTIAL WP3: Links with other WPs and Tasks 76 MODERN 2010 Review March 1st, 2011 WP2 T2.4 T2.3 WP4 T4.1 T4.2 T5.2T5.3 WP5 T5.1 ST I, UNRM WP3 T3.1 T3.2 T3.3 T3.4 ST I NXP UPC, LETI IFX,LETI NXP T4.4 UPC T2.5

CONFIDENTIAL Task T3.1: PV-aware circuit models Progress, high- and lowlights Partners: TUD, LIRM, NXP, ST-I, TUE, UNRM Process variation will be included in existing physical and symbolic circuit models. These models are essential to effectively predict delay variations in order to be able to design reliable and predictable electronic circuits. D3.1.1NXP, ST-I, TUD, TUE, UNRM: Set of alternative symbolic models for lib cells D3.1.2 LIRM, NXP, ST-I, TUD, TUE, UNRM (M24) Statistical methodology for characterisation of digital and AMS&RF circuits Highlights –Implicit model for probabilistic sets of waveforms –Prototypes for automatic reduction of large RC networks –In depth verification of statistical standard cell library –Reliable results with Support Vector Machine –SSTA Framework based on moments propagation. 77 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T3.1 Statistical Analysis of On Chip Timing Variation 78 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 79 Red: Surrogate model outputs Blue: Original outputs Good performance of surrogate models on the test set Output START_PH1: Comparison on the test set A larger experimentation of surrogate models is in order; New input-output data sets for different circuits are expected from ST-I; Results of main interest for task T3.2; Cooperation between UNRM and ST-I essential. T3.1: surrogate behavioral models The optimization procedures considered in T3.2 requires the availability of a circuit simulator (e.g. SPICE). Each simulation run may require a large computing time; GOAL in T3.2: development of surrogate models for the circuit behaviour based on learning machines (e.g. Neural Networks, Support Vector Machines); So as to employ the surrogate model instead of the circuit simulator. 79 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 80 Partners: UNBO, NMX, NXP, ST-I, UNCA, UNGL, UNRM To compensate for process variation during circuit design the PV-aware circuit models need to be used in new methods for circuit design and future design tools and flows D3.2.1 ST-I, UNBO, UNCA, UNRM: Circuit techniques, and speed-up algorithms for PV-aware circuit simulation D3.2.2 NMX, NXP, UNBO, UNCA, UNGL, UNRM: Standardized PV-aware tools for simulation of digital blocks, AMS&RF blocks, and NVM arrays (M24) Highlights: –ABB tested in 65nm, 45nm, 32 nm –Improvements in delay and energy consumption observed by applying transistor ordening combined with dual threshold –Sense amplifier circuit has been evaluated with Random Spice –Actvity analysis tool to identify impact on critical path T3.2: Methods, Tools & Flows Progress, high- and lowlights MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T3.2: Analysis of Analogue Sensing Memory Circuit with RandomSpice Adapted Sense Amplifier circuit of NMX analyzed with RandomSpice (UNGL) SPICE frontend for advanced statistical circuit simulation. Allows use of UNGL-developed PCA and non-linear power method compact model parameter generation methods. Statistical enhancement of circuit simulation to access very rare circuit instances. Database and post-processing backend for power/performance/yield predictions. In parallel results are compared with different methodologies for validation purpose 81 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 82 Partners (underlined task leader) : POLI, CSEM, IFXA, LETI, UPC Solutions for PV-aware circuit design are proposed by either a monitor & control strategy or by development of low PV sensitive standard cell libraries. Inherently variability robust designs are introduced by restricted design rules, redundant/spare transistors and self-timed logic. D3.3.1 CSEM, IFXA, LETI, POLI, UPC: PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital and AMS&RF D3.3.2 CSEM, IFXA, LETI, NXP, POLI, UPC: PV-tolerant lib cell designs and M&C implementation in digital and AMS&RF (M24) Highlights: –parameterized tunable sleep transistor cells lib –Monitoring structure designed in 32nm –Design of the regular fabric VCTA (Via Configurable Transistor Array) –Architecture of Turtle Logic T3.3: PV-aware design Progress, high- and lowlights MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T3.3: M&C Strategies for AMS & RF Switches –Monitor concepts: ring oscillator, current sensing –Control: “frequency locked loop”, analog control loop Aging induced offsets –Avoid offset generation: e.g. chopping (comparator) –Correction of static & dynamic effects: e.g. error correction by redundancy –Burn-in: dedicated stress to increase robustness and compensate PV 83 ADC search algorithm incl. redundancy 83 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T3.3.2: PV Monitor “Stability Checkers” sensors – Timing Faults anticipation – Transition detection in a window – Shared by several paths  Monitor : 3.2 x 1.2 µm²  clockcell : 5.7 x 1.2 µm² 84 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Specific Flow set-up Critical paths selection during back-end Reduction of the number of paths to monitor (from 50% to 3%) Post-Placement sensors insertion Specific cells at the leafs of the clock tree Final routing Sensors Timing check At calibration : maximum possible frequency can be reached (no worst case) Window1 : 87%-98% Fr max possible Window2 : 84%-93% Fr max possible T3.3: LETI’s PV Monitor (3) 85 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 86 Partners : NXP, LIRM, ST-I Next to process variation there is also a large contribution to the timing variation from EMI/EMC related issues. Additionally, due to miniaturisation and co-habitation of AMS&RF the analogue circuits risks suffering from the digital noise. New design techniques will be proposed to suppress and canalise noise and EMI for improved reliability of the complete electrical system. D3.4.1 LIRM, ST-I: Impact of supply noise, and clock distribution on EMI and circuit timing D3.4.2 NXP: RF-interaction models for combined PCB-package-IC D3.4.3 NXP, ST-I: Substrate RF coupling, RF co-simulator, Power Distribution Model (PDN) evaluation and analysis flow for combined IC-package-PCB (M24) D3.4.4 ST-I:Implementation and evaluation of clock tree synthesis techniques for low EMI (M24) Highlights –Design flow for substrate noise analysis –De-embedded Substrate noise measurement results correlate with 3 rd party analysis tool –Successful implementation of circuit level lumped-element model of PDN –Encouraging results on EMI reduction by EMC-aware CTS techniques T3.4: Design for low noise and EMI/EMC Progress, high- and lowlights MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 87 T3.4: Neptune 5 test chip specs Spectrum of the output of FM buffer with and without digital noise present in the system Current floor plan proposal Links to WP5, demonstrator test-chip on substrate noise MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 88 T3.4: Substrate extraction flow in SOI *functionality in red is added to the standard flow Disturbed output of the bandgap due to noise propagation through the substrate MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP3 Cooperation Face to face meetings –General WP3 Meeting in Catania, representation of almost all participants (11/15) Agreements on Domain overview per task Clarified links between task and WP’s –Several meetings for Dutch and Italian partners Regular telco meetings and e-mail contact –Italian partners –Dutch partners –LIRM/LETI –NMX/UNGL –UPC/IFX –NXP/NMX 89 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP3 Dissemination Events: –VARI conference, organized by LIRMM Publications: –T3.1: Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, A Simplified Transistor Model for CMOS Timing Analysis, Proceedings of ProRISC 2009 Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis, Proceedings of DAC 2010. Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Statistical Moment Estimation in Circuit Simulation, Proceedings of VARI 2010, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Transistor Level Waveform Evaluation for Timing Analysis, Proceedings of VARI 2010. Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Transistor-Level Gate Modelling for Nano CMOS Circuit Veriﬁcation Considering Statistical Process Variations, PATMOS 2010. Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, Noise Analysis of Non-Linear Dynamic Integrated Circuits, Proceedings of CICC 2010. Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, Discrete Recursive Algorithm for Estimation of Non-Stationary Noise in Deep-Submicron Integrated Circuits, Proceedings of ICSICT 2010. Amir Zjajo, Qin Tang, Jose Pineda de Gyvez, Michel Berkelaar, Alessandro Di Bucchianico, Nick van der Meijs, Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs, IEEE Transactions on Circuits and Systems-I: Regular Papers, in press Ashish Nigam, Standard Cell Modelling for Timing Analysis, Technical Report TU Delft. (Report/Thesis) Ashish Nigam, Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis, M.Sc. Thesis TU Delft. (Report/Thesis) –T3.2: [1] Alpaslan, E.; Dworak, J.; Kruseman, B.; Majhi, A.K.; Heuvelman, W.M.; van de Wiel, P.;, "NIM- a noise index model to estimate delay discrepancies between silicon and simulation," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, vol., no., pp.1373-1376, 8-12 March 2010 –T3.3: M. Pons, F. Moll, A. Rubio, J. Abella, X. vera, A. González, “VCTA: A Via-Configurable Transistor Array Regular Fabric”, VLSI-SOC 2010. L. García-Leyva, A. Calomarde, F. Moll, A. Rubio, “Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits”, MWSCAS 2010 –T3.4 F. Campi, T. Bjerregaard, M. Stensgaard, and D. Pandini, “Power Shaping Methodology for Supply Noise and EMI Reduction,” Design Automation Conf., Jun. 2010. 90 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP3 Dissemination Submitted papers –T3.1 Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, Adaptive Numerical Integration Methods for Deterministic Analysis of Non-Stationary Noise in Dynamic Integrated Circuits, submitted to ASP-DAC 2011 Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Pseudo Circuit Model for Representing Uncertainty in Waveforms, submitted to DATE 2011 Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Statistical Moment Estimation of Delay and Power in Circuit Simulation, invited and submitted to Journal of Low Power Electronics. 91 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP3 Other issues, Q&A 92 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP4: Outline Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ Link with other WPs and Tasks, Cooperations Dissemination (publications, patents), exploitation Other issues, Q&A 93 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP4 Task Structure Variability- aware circuits Design flows for reliability Reliable architectures Regular Fabrics Robust reconfigurable systems T4.1 T4.2 T4.3T4.4 T4.5 Adaptive circuits Monitors Design flows De- synchron ization methods and libraries Reliable NVM Redund ancy in AMS Redund ancy in MPSoC Regular, Mask Program mable systems. Robust MPSoc, Robust program ming paradigm. 94 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP4 M24 Deliverables 95 D4.1.1LETI, UPC Reports on PV-aware (self-) adaptive compensation and optimization techniques, including on-chip monitors D4.2.2 TMPO, LETI, TEKL Reports on PV-tolerant noise and EMI reduction techniques, and on asynchronous and de-synchronized communication scheme benchmarking D4.2.3ELX, POLI Advanced asynchronous/de-synchronization flow. Delivery of the first de- synchronized design D4.3.2NMXNVM design and robustness assessment report D4.3.3ISD, THL Functional and test specs for a validated controller for ADC and PLL components. Fault-tolerant on-chip global communication scheme on a multi-core SoC virtual platform D4.4.1UPC, TMPO Report on yield prediction tool and regular structures for PV-tolerant asynchronous blocks D4.4.2ST I, UNBO Report on customizable and regular architectures [….] Delivery of a design flow for mapping on mask-programmable computational blocks […] D4.5.1THL, LIRM Report on programming methods and tools for PV-tolerant, reliable, and predictable MPSoC architectures MODERN 2010 Review March 1st, 2011 All M24 deliverables completed according to milestones, No major criticality detected/reported

CONFIDENTIAL WP4 Domain Overview per Task and Partner 96 T4.1T4.2T4.3T4.4T4.5 Digital IPs/macrosUPC, LETIST I, UNBO Analog/AMS IPs/macrosUPC, LETIISD Asynchronous IPs/macros/cells TMPO, LETITMPO Regular/configurable IPs/fabrics ST I, UPC Architectures/Micro- architectures LETI ISD, THL, ST F, NMXST I, UNBOLIRM Interconnect schemes and on-chip communication LETIISD, THL, ST F CAD flows and integrationELX, TMPO, TEKL, POLIST I VariabilityLETI, UPCELX, TMPO, LETITMPOLIRM EMC/EMIELX, TMPO, TEKL, POLI, ST I Reliability/Fault toleranceISD, THL, ST F, NMXTHL Manufacturability and yieldST I,UPC, UNBO, TMPO ReconfigurabilityST F, THL, ISDUNBOLIRM, THL Software and programming methods ST I, UNBOLIRM, THL MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP4 Technology Overview per Task and Partner 97 TechnologyT4.1T4.2T4.3T4.4T4.5 90nm + eNVM POLI, ST I, TEKL, ELX 65nmUPCTMPOST F, ISD UPC, ST I, UNBO, TMPO LIRM 45nmLETI 40nmELX, TMPOISDST I, UPC, TMPO 32nmLETI THL NVMNMX MODERN 2010 Review March 1st, 2011

CONFIDENTIAL D4.1.1: PV-aware adaptive compensation techniques (1) LAVS (Local Adaptive Voltage Scaling Architecture) –Monitor / Adapt V,F using Delay-based Diagnostic system Adaptation controller Local Power Manager 98 MODERN 2010 Review March 1st, 2011 –Advantages: Operate on local, realistic silicon corner (vs wc analysis) Monitor/adjust to variations along circuit lifetime Optimize timing / power

CONFIDENTIAL Study of Delay-Based Variation Control using Body Bias (BB) and Voltage Scaling (VS) –Variation is Monitored using on-chip sensors: Leakage / Dynamic Power / Delay –Based on sensor information, BB and VS is applied to reduce variability –Study of correlation between observables: Delay distributionDelay distribution shows larger correlation Use of delay sensors can reduce not only delay variability, but also leakage and dynamic power variability Voltage Scaled Elastic clock architecture (with task 4.2) –Elastic clocks allow clock period margin reduction Objective of analysis is to quantify this reduction with respect to Voltage noise Study of correlation between voltage at several chip locations. 99 MODERN 2010 Review March 1st, 2011 D4.1.1: PV-aware adaptive compensation techniques (2)

CONFIDENTIAL D4.2.2: PV-tolerant noise and EMI reduction techniques (1) QDI asynchronous NoC based on Muller gates: fully designed in STM 32nm technology GALS interfaces to communicate with synchronous IPs: –2 Macros: Target / Initiator –Performance Noc Area: 108 µm x 60 µm Asynchronous Peak : ~1GHz @tt32_1.00V_25C Interfaces : 800MHz @tt32_1.00V_25C Latency : 1 router : 0.8 ns initiator to target : 1.6 ns 100 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL “Power shaping” methodology and design flow for power robustness and low-EMI –Uses standard indudstry formats (Verilog, SDF SDC), exports modified Verilog + flow specific clock tree synthesis directives. –Proposed methodology applied to a 90nm IC reference design provided by ST-I. 101 MODERN 2010 Review March 1st, 2011 Smooth design flow integration 28% reduction of IC pad current peaks. 25% reduction of Max Dynamic Voltage Drop. 55% reduction of IC pad voltage fluctuations. Up to 30 dBµV reduction of digital core conducted EMI harmonics Flow is now under formal evaluation by ST on 2 different product lines D4.2.2: PV-tolerant noise and EMI reduction techniques (2)

CONFIDENTIAL Variability-tolerant low-EMI asynchronous circuits: flow to design PVT- tolerant asynchronous cells –Consolidated cells and macro-blocks (65 nm full Library [ + 45 nm library + RAM & ROM) –Realized flow to estimate current consumption profile and estimate EMI –Demonstrated the efficiency of the approach on asynchronous ciphering IPs like DES and AES, Compared with synchronous design –Further attenuation made available by delay insertion (2.6x in time domain, 10dB in frequency domain 102 MODERN 2010 Review March 1st, 2011 Asynchronous circuit model SystemVerilog Synthesis Simulation current estimation Delay adaptation SystemVerilog circuit model Li b D4.2.2: PV-tolerant noise and EMI reduction techniques (3) Synchronous Asynchronous 4 mA 1.2 mA Asynchronous 60 dBµ Synchronous 80 dBµ

CONFIDENTIAL D4.2.3: Advanced De-synchronization Flows (1) 103 MODERN 2010 Review March 1st, 2011 Automated block-level de-synchronization of synchronous netlists –Exploits existing Synthesis / P&R Tools –Synthesis of matched delays Delay lines track circuit variability of the circuit at multiple corners and voltages Delay synthesized using standard cells Tracks high-frequency variability (e.g. dynamic voltage fluctuations) –Sign-Off flow Flow requires specific sign-off procedure, based on synchronous setup/hold constraints. Implemented in existing STA tools –Results: AES cipher module (10K gates,17000 µm 2, 40nm) 35% reduction vs nominal case. 21% reduction vs standard voltage scaling Robustness: de-synchronized circuit tracks hi-freq voltage fluctuations (> 200mV) that lead to Synchronous circuit fails MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Asynchronous High-Level Synthesis (AHLS) –Same SystemC model as synchronous (untimed or with TLM-style handshaking) Standardized entry point vs Handshake Solutions Lower power vs de-synchronization –No clock: Resources controlled by handshaking Based on Petri net formulation –Status Available: Petri net construction from DFG, State exploration, scheduling Future Work: advanced pruning optimizations, comparison with other AHLS / Synchronous, DFG generation from SysC, netlist generation for BE 104 MODERN 2010 Review March 1st, 2011 D4.2.3: Advanced De-synchronization Flows (2) mul2 3 1 add2 1

CONFIDENTIAL D4.3.2: NVM Reliable Design 105 High level architecture of the decoder Comparison of different concatenation schemes to: Minimize parity check bits Achieve high reliability target (UBER < 10 -15 ) Have reasonable latency overhead Current best solution: LDPC+BCH Preliminary analysis: concatenation of two codes Inner code: to improve the “channel” reliabilityOuter code: to “crunch” all the errors MODERN 2010 Review March 1st, 2011 Two independent ECC levels –Ci: Soft Decoded LDPC: –Fully parallel solution Needed RAM: 2 x 4 x 212 bits ~ 10 iterations, 450 “check machines” (each check involves ~40 bits) –Note: need for processing the whole WL even if one ECC block is requested –Co: BCH: 32-bit parallel hard decoded architecture Soft Code Reliability info based on a predictive model (wp2) tuned on experimental data MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Design methodology for Reliable Multi-cores: –Homogeneous multi-core systems equipped with spare elements for transparent and deterministic workaround of local permanent faults –Hardware level exploit hardware redundancy and fault control: –Computation Resources: processor cores –Storage resources: memory tiles and clusters –Routing resources: physical links, router and network interfaces. –System and application level (Link with Task 4.5.1) fault tolerant parallel programming paradigms possibly assisted by hardware extensions robust real-time operating system and algorithmic fault tolerance at user-level 106 MODERN 2010 Review March 1st, 2011 D4.3.3: Fault Tolerant Design (1)

CONFIDENTIAL Design methodology for Reliable Multi-cores: –Fault Tolerant Multicore Platform based on dynamic redundancy control in-situ characterization (BIST/BISR) non-intrusiveness of monitoring process uninterruptible system operation Results: –Pedestrian recognition developed on the SysC multicore architecture –Characterized impact of task relocation and simulated faults (Correct results, Low impact on latency, no impact on throughput) D4.3.3: Fault Tolerant Design (2) 107 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL D4.3.3: Fault Tolerant Design (3) RTL implementation of fault tolerant routing on interconnect schemes –Deployed on Spidergon STNoC technology –adaptive fault tolerant routing through re-programming network interface routing registers, dramatically reducing the consequences of link and router faults –As a side benefit, this introduces more freedom in dynamic modifications of network topology, enhancing NoC flexibility Usage planned on STMicroelectronics and ST-Ericsson platforms 108 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Design and implementation of a dynamic controller for test, detect and repair faulty analog mixed signal (AMS) IP –Design methodology based on dynamic redundancy control in-situ operational characterization (BIST/BISR) non-intrusiveness of monitoring process, uninterruptible system operation 109 MODERN 2010 Review March 1st, 2011 Status: Developed behavioral models of PLL/ADC with process variation in SystemC- AMS Performed functional validation and sensitivity analysis Determined preliminary metrics (eventually tp be linked to electrical parameters) to characterize the operational range of AMS component This will eventually lead to full operational characterization of the IPs D4.3.3: Fault Tolerant Design (4) MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 110 D4.4.2: Customizable regular architectures (1) gnd vdd Configuration through via connections Via programmable datapath for fast SoC design –Pipelined array of identical pre-Layouted arithmethic / logic operators [200MHz @ 65nm] –Functionality & Routing Customized by VIA4 connection [1 Mask] Design flow: from C-level DFG description [GriffyC] to programmable array configuration: –Implementation of the design flow front-end architecture. –Implementation of flow for RTL generation from Griffy-C description –Implementation of back-end flow for via programmable datapath configuration MODERN 2010 Review March 1st, 2011

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 111 Design flow: from C-level DFG description [GriffyC] to transistor array configuration –GriffyC to RTL –RTL to P&R –P&R to mask configuration Mask programmable Transistor Array –Base Regular Cell with 4 Transistors –Customization through M1/M2 Connections –Advantages: Increased Yield Mask Cost reduction for Different Customizations D4.4.2: Customizable regular architectures (2)

CONFIDENTIAL Development of architecture & programming model for application mapping on regular multiprocessor architecture –Hierarchical Multi-Many Core architecture –Thread level parallelism –Heterogeneous, Distributed ASIC Acceleration mapped on identical mask programmable macros Development of a hardware/software design methodology for application mapping and accelerator design –customizable System-C simulator –customizable RTL model –Automated generation of accelerator layout based on mask programmed technology MODERN 2010 Review March 1st, 2011 112 D4.4.2: Customizable regular architectures (3)

CONFIDENTIAL D4.5.1: Methods and tools for PV-tolerant, reliable and predictable MPSoC (1) Fault tolerant HW/SW integrated model for Many core SoC –From Coarse-grained DFG description, produce fault- robust C -code suitable for datastream applications having predictable fault reaction on MPSoC –Run functional (High level) and timed systemC simulation allowing the user to predict performance loss in any given fault scenario MODERN 2010 Review March 1st, 2011 113

CONFIDENTIAL Runtime task remapping in homogeneous MPSoCs –Distributed MPSoC architecture, from high-level model to hardware prototype –Distributed memory MPSoC System is capable of adapting itself to perturbations –Self-adaptive task migration Monitors: CPU load, FIFO usage –Dynamic Frequency scaling Fault tolerance mechanism –Based on “watchdog” techniques –Each PE monitors neighbours –Diagnostics, isolation and recovery MODERN 2010 Review March 1st, 2011 114 D4.5.1: Methods and tools for PV-tolerant, reliable and predictable MPSoC (2) FPGA-based prototype SystemC Model

CONFIDENTIAL WP4 Exploitation plan (1) In T4.1 cooperation between LETI and UPC on the temperature monitoring activity, and to coordinate the activities of both institutions in MODERN. Collaboration between LETI and ST F on technology transfer In T4.1 cooperation between ELX and UPC on voltage variation measurements across chip In T4.2 cooperation between ELX, POLI, and ST I on the design flow for desynchronization and on EMI reduction techniques In T4.2 cooperation between TEKL and ST I on the power shaping methodology for EMI reduction and flow definition and integration of TEKL’s tool into ST design flow In T4.2 cooperation between LETI and TMPO on QDI asynchronous logic implementation 115 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP4 Exploitation plan (2) In T4.3 common research activities and cooperation between ISD and THL, and between THL and ST F on reliable chip level interconnect In T4.3 cooperation between ST F, ST I and UNBO on STNoC technology utilization In T4.4 cooperation between ST I, UPC and TMPO on the evaluation of the impact of regular design In T4.4 ST I and UNBO are cooperating on a design flow for mapping applications on mask-programmable computational blocks, regular transistor arrays, and via-/metal-programmable datapaths In T4.5 cooperation between LIRM and LETI on fine-grain power optimization under variability, cooperation between LIRM and ST F on MPSoC fault tolerance 116 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP4: Links with other WPs and Tasks 117 WP3 T3.3 WP4 T4.1 T4.2 T4.3 T4.4 T4.5 WP5 T5.2 T5.3 UPC, LETI LETI, TMPO UPC, TMPO, ST I THL THL, LIRM T3.4 ST I MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Published Papers F. Campi, T. Bjerregaard, M. Stensgaard, and D. Pandini, “Power Shaping Methodology for Supply Noise and EMI Reduction,” Design Automation Conf., Jun. 2010. I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. VARI, May 2010 C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio,” in Proc. Intl. Symp. on VLSI, Jul. 2010. C. Jalier, D. Lattard, A. A. Jerraya, G. Sassatelli, P. Benoit, and L, Torres, “Heterogeneous vs. Homogeneous MPSoC Approaches for a Mobile LTE Modem,” in Proc. DATE, Mar. 2010. J. Altet, D. Gómez, C. Dufis, J. L. González, D. Mateo, X. Aragonés, F. Moll, and A. Rubio, “On Evaluating Temperature as Observable for CMOS Technology Variability,” in Proc. VARI 2010, May 2010. J. Cortadella, L. Lavagno, D. Amiri, J. Casanova, C. Macián, F. Martorell, J. A. Moya, L. Necchi, D. Sokolov, and E. Tuncer, “Narrowing the Margins with Elastic Clocks,” in Proc. Intl. Conf. on Integrated Circuits Design and Technology, Jun. 2010. C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “Flexible and Distributed Real-Time Control on a 4G Telecom MPSoC,” in Proc. ISCAS, Jun. 2010. I. Mansouri, C. Jalier, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. Intl. Symp. on VLSI, Jul. 2010. I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “A Run-time Distributed Cooperative Approach to Optimize Power Consumption in MPSoCs,”, in Proc. Intl. SOC Conf., Sep. 2010. N. Hebert, P. Benoit, G. Sassatelli, and L. Torres, ‘’D-Scale: A Scalable System-level Dependable Method for MPSoCs,’’ in Proc. Asian Test Symposium, Dec. 2010. M. Pons, F. Moll, A. Rubio, J. Abella, X. vera, and A. González, “VCTA: A Via-Configurable Transistor Array Regular Fabric”, VLSI-SOC 2010. N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, “Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” in Proc. VARI, May 2010. N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, "Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” JOLPE, vol. 6, n. 4, Dec. 2010. Submitted Papers 2011: IEEE DATE (LIRM), IEEE ISCAS (LIRM) 118 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP4 Summary Several WP4 meetings to prepare M24 deliverables –F2f meetings ELX/UPC on July 12 th and 19 th and on October 5 th, 2010. –F2f meeting ST Catania Nov. 9 th –Three web meetings (Sep. ‘10, Dec. ‘10, Jan. ‘11) Demonstrators –System MPSoC platform, with task migration, failure analysis, power optimization considering variability effects, and HW implementation of several blocks to propose online optimization – LIRM T4.5 All M24 deliverables completed according to milestones –No major criticality detected/reported by task leaders and partners 119 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP5 agenda Progress, highlights and lowlights Structuring of demonstrators: goals and objectives Link with other WPs and Tasks, Cooperation Dissemination (publications, patents), exploitation Technical status and achievements of deliverable D5.1.2 (incl. changes) Contents of D5.3.2 (M24) Other issues, Q&A 120 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL WP5 Progress, highlights and lowlights Globally WP5 activities are on track Second year deliverable achieved: D5.1.2 (see dedicated section) Good progress on detailed demonstrator definition achieved as a results on the activities progress in the “mother” work packages Different technologies and technologies nodes are involved During Catania meeting cooperation strenghtened M24 deliverables on traks (considering ST-I shift from M24 to M36) Possible issues for Tiempo testchip recovering action under study 121 MODERN 2010 Review March 1st, 2011 121 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Structuring of demonstrators: goals and objectives 3 technological areas involved and different technological nodes (65, 40, 32, 28nm) research areas Logic CMOS RF / AMS Power Reliability Aging Noise Performance Robustness Monitoring (T3.3) Redundancy (T3.3) Adaptation (T4.1) Regularity (T4.4) Robust architectures (T4.5) Monitor & Control (T3.3) Model verification (T2.4-T2.5) 122 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Test chip plan: owner UPC Technology 65nm (CMP): –Low Noise Amplifier with Temperature monitoring –Voltage Controlled Oscillator with monitor and control (T3.3) Technology 40nm (CMP): –Design of Voltage Controlled Delay Line VCDL and Digital Locked Loop –Via Configurable Transistor Array application for variation impact of regularity (T4.4) 123 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Test chip plan: owner LETI; Architecture Overview A fine grain Local Dynamic Adaptive voltage and frequency scaling architecture Diagnostic: –Process-Voltage-Temperature –Timing fault detection or prevention (T3.3) Actuators: –Based on Vdd-hopping –Local clock generation using FLL Power/Variability Control –Local control with minimum hardware (T4.1, T4.2) –Global control : high level algorithms to minimize power consumption PE CVPU ANOC RunTime 0.9v 0.7v PE CVPU 0.9v 0.7v Main HW objective : a minimum hardware based on standard cells and simple analog macros for flow insertion and maximum efficiency 124 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Test chip plan: owner LETI; LoCoMoTIV flooplan 32nm technology CDMA PE0 PE1 PE2 PE3 ANOC L2RAM Hopping transition and switches : Voltage genration PVT probes Fully digital FLL : Frequency generation 125 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Test chip plan: owner AMS Task 5.2 - TUG Design and fabrication of benchmark structures. Validation of proposed benchmark cases. Outstanding deliverables: –D5.2.2 – M27 –D5.2.3 – M36 Benchmark Structures Benchmark Cases Rel. Simulator Hu derivative Rel. Simulator TUV analytical model MINIMOS-NT Reliability WC models hierarchically structured Structure 1 ☺/X Structure 2 Structure 4 etc. 126 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Test chip plan: owner IFXA Objective: development and verification of monitor & control (M&C) strategies for AMS&RF circuits to deal with aging/reliability issues and aging induced parameter variations in nanometer CMOS. Close link to T3.3 (M&C concept development) Outline –Basic aging/reliability assessment  identify sensitivities Aging simulations (proof of sim.-concept, model-hardware correlation in T5.2) Dedicated test-structures for transient effects and aging-parameter-variations –Development of M&C concepts  T3.3 –Implementation and verification of M&C concepts Silicon based proof of concept Concept development for accelerated aging/stress tests  T5.2 Development of characterization methods (fast transient effects)  T5.2 Test-chip status: –TC #1 (32nm CMOS): taped, lab characterization completed –TC #2 (32nm CMOS): taped, lab characterization on-going –TC #3 (28nm CMOS): design just finished, ready for taped-out 127 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Test chip plan: owner IFXA Status implementation & verification of M&C conceptsM&C concepts –Accelerated aging test-setup proven on TC1 and TC2 (OpAmps, VCOs) –Fast offset characterization method (transient effects) proven on TC2 –Measurements to be finalized on TC2 ADC incl. error correction (static & transient offsets) Switch degradation monitor circuits Variations of aging parameters Novel burn-in concept (to increase robustness and compensate PV) with a dedicated stress pattern –Macros implemented on TC3 Switch control circuits to be implemented on TC3 DCDC test-structures 128 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Test chip plan: owner NXP (Neptune 5) Spectrum of the output of FM buffer with and without digital noise present in the system Current floor plan proposal 129 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Cooperation and dissemination Published / papers: –L. Bortesi, L. Vendrame, G. Fontana “Combined test structure for systematic and stochastic Mosfets and gate resistance process variation assessment” Proc IEEE-ICMTS, pp.226-230 (2010 IEEE International Conference on Microelectronic Test Structures, March 22-25, Hiroshima, Japan). 130 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL T5.1 Test structures and D5.1.2 Partners: AMS, NMX, STF2, TUG Technologies: –45nm CMOS technology developed by STMicroelectronics –Non volatile memory technology from Numonyx –HV-CMOS technology working up to 120V from Austriamicrosystems T5.1 peculiarities, Goals and Obiectives: –Feed data to other WPs / verify estimation –Define improvement in test structures to increase accuracy –Development of advanced Mismatch test - structures –Development and Evaluation of PV Monitoring structures and Methods Innovative aspects / returns: –Applications of same concepts to different technologies with smart adaptations – Higher accuracy in PV simulation results in silicon area savings –Applicable for Product design with possible increase in Yield Links between WPs and tasks: –T2.3: SPICE Monte Carlo models –T2.5: PV-aware compact modeling –T2.1 and T2.2: T5.1 will deliver the benchmark for process and device simulation –The experimental results (NMX restricted) will be used for comparison with simulations for the validation of NMX methodology studied within WP3, T3.2, D3.2.3 (M36) 131 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 132 D5.1.2 achievements Task 5.1 – AMS, TUG Focus of D5.1.2 is the design and layout of: –analog monitoring and characterization parameter structures –monitoring structures utilizing Kelvin-Probe measurement technique for standard and butted devices –matching test structures for HV-FETS: with standard pad-sharing approach with terminal multiplexing matching test structures Delivered with one month extension for reporting 132 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Example I: MOSFET Monitoring Structure utilizing Kelvin-Probe Measurement Technique Realization for standard devices Compensation of voltage drops due to wiring Pad utilization of adjacent unobserved devices for the sense line reduce area consumption “Sense” devices are active but currentless 133 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Example I: MOSFET Monitoring Structure utilizing Kelvin-Probe Measurement Technique Realization for devices which are aimed to work at Vbs=0V S & B commonly connected with metal attention to unwanted short-circuits Device area reduction due to missing FOX between source and bulk especially for short channel devices A…gate line 1 B…gate line 2 C…sense line between drains 3…drain pad 1 6…drain pad 2 4…source/bulk pad 5…source/bulk pad 134 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Example II: 5.2. Design of terminal multiplexing matching test structures for HV-FETs Basis for matrix structure is given by standard pad sharing structure for HV-FET matching characterization Consideration of “golden rules”: symmetry, current direction, symmetric connections, usage of guard rings etc. Final structure for characterization is realized as matrix consisting of equidistant placed devices 135 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Example II: 5.2. Design of terminal multiplexing matching test structures for HV-FETs Development of multiplexer test-structure for distance dependent matching characterization of HV-FETs Utilization of Kelvin-technique applied to individual transistor pairs within the matrix Consideration of voltages up to 50V, which is a typical voltage level for HV-LDMOS FETs Design of special transmission gates (switches) for gate and drain terminal multiplexing Facts: –208 HV-switches for gate bias multiplexing –24 HV-switches for drain bias multiplexing –Maximum drain current Imax = 20mA 136 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL Contents of D.5.3.2 (M24) Partners: SNPS, NXP Title: Prototype implementation of geometrical variation model (by SNPS). Software prototype implementation of parameterized design methodology and MOR for parameterized problems Synopsys: implementation of Impedance Field Method (IFM) in Sentaurus Device for the physical modeling of geometrical PV effects in three spatial dimensions. The advantages of the approach to calculate the geometrical fluctuations via IFM are connected with meshing, mesh noise, simulation stability and computation time. NXP: parameterized design methodology. Key components: –Creating parameterized designs by programming instead of manually designing chip layouts –automatic optimization of parameterized designs for performance at extracted layout level –reduction of extracted layouts by model order reduction 137 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL MODERN 2010 Review March 1st, 2011 138

MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31) WP1: Giuliana GangemiWP2:

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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31) WP1: Giuliana GangemiWP2:

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Presentation on theme: "MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31) WP1: Giuliana GangemiWP2:"— Presentation transcript:

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