1. 1 VERILOG Fundamentals Workshop סמסטר א ' תשע " ה מרצה : משה דורון הפקולטה להנדסה Workshop Objectives: Gain basic understanding of the essential concepts and capabilities of Verilog HW Description Language (HDL) Demonstrate Verilog code for Digital Systems and Simple Processor Design Focus on Behavioral and Data Flow Abstraction Levels - Register Transfer Level (RTL)

2. 2 General Information ספרות – ספרים בספריה Verilog HDL: A Guide to Digital Design and Synthesis Design Through Verilog HDL A Verilog HDL Primer Digital VLSI Design with Verilog אתר אינטרנט http://www.asic-world.com/verilog/intro1.html חובה להגיש את כל ארבעת התרגילים. בבחינת הקורס כולו, תהיה שאלת תכנון לוגי בשפת וורילוג.

3. 3 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling A Workshop 10 - Behavioral modeling B Workshop 11 - Behavioral modeling C Workshop 12 - Data flow modeling Workshop 13 - Coding Styles

4. 4 What is Verilog HDL and it’s design advantages A single language for Design and Simulation, IEEE STD 1364 C- based Syntax, easy to master and use Condensed and efficient code Intensively used by Israeli Hi-Tech Industry A convenient, powerful, Device-independent representation of Digital Logic (Behavior and Structure) Boosts Design Methodology: Functionality can be verified early in the design process. Simulation at a higher level, enable architectural evaluation of new design ideas, explore several approaches to design problems and make decisions Coupling Verilog Compiler with Logic Synthesis tools, automatically converts a Technology-independent HDL Design description and Functionality to a Gate-Level implementation, in different target Technologies.

5. 5 Language Capabilities Verilog, as a High-level Language, has constructs supporting various Design’s Abstraction Levels: Behavioral, Dataflow, Gate and Switch level Design can be modeled in a mixed Abstraction Levels Hierarchical design can be described, up to any level, using the module instantiation construct A design can be of arbitrary size. No limit imposed Two data types: net (wire) & variable (reg - abstract data storage element) Primitive Logic Gates and Switch-Level Gates, are built-in Language used for Test Bench - Stimuli & Monitor results Flexibility of creating a Combinational or Sequential, User Defined Primitive (UDP)

6. 6 Levels of Abstraction Verilog Abstraction Levels (Top-to-Bottom): Behavioral - A module is implemented in terms of desired algorithm, without knowing the HW implementation details. Data Flow- A module is designed by specifying the data flow between registers and how data is processed. Register Transfer Level (RTL). Gate Level- A module is implemented in terms of built-in and UDP logic gates and the interconnections between them. Switch Level- A module is implemented in terms of switches (transistors), storage nodes, resistors and the interconnections between them.

7. 7 Design Flow using Verilog Structure and Function (Behavior) of the Design Design Behaves as Required ? Timing : Waveform Behavior Mapping Verified Design to target HW - FPGA or ASIC Efficient, well-documented coding Translate Verilog HDL description, into Netlist Compilation Simulation & Verification Specification Architecture Design Coding in Verilog Synthesis Mapping Logic Optimization Function/Performance Definition

8. 8 Design Methodologies

9. 9 Basic Unit – The Module Verilog describes a digital system as a set of modules Element or a collection of lower level design blocks A module can be instantiated in another module Each module has an interface and content description Modules communicate externally via input, output and inout bi-directional ports

10. 10 Module Structure module module_name (port_list) ; declarations: port declaration (input, output, inout, …) data type declaration (reg, wire, parameter, …) task and function declaration statements: initial block always block module instantiation gate instantiation UDP instantiation continuous assignment endmodule Behavioral Structural Data-flow

11. 11 Example - AND module (data flow & behavioral) module AND (out, in1, in2) ; // input in1, in2 ; output wire out ; assign out = in1 & in2 ; // data flow - continuous Assignment endmodule out in1 in2 module AND (out, in1, in2) ; // input in1, in2 ; output reg out ; /* Implicit, not a real register, when used as LHS in an always block */ always @( in1 or in2) // always block (sensitivity list) - behavioral out = in1 & in2 ; /* statements inside always block are executed only when one or more signals in the list changes value */ endmodule

12. 12 AND module – Simulation results

13. 13 Example – D_FF (behavioral) module module D_FF(clk, nrst, d, q) ; input clk, nrst, d ; output reg q ; always @(posedge clk or negedge nrst ) // Event-based Timing Control if (!nrst) // Reset state q <= 0 ; else // Normal operation q <= d ; endmodule D Q clk nrst

14. 14 D_FF Simulation results