1. Technical University Tallinn ESTONIA 1 Otsustusdiagrammide kasutamisest digitaalsüsteemide diagnostikas Raimund Ubar TTÜ, Arvutitehnika instituut Tartu Ülikool, 23. mai 2003

2. Technical University Tallinn ESTONIA 2 Ülevaade: Digitaalsüsteemide diagnostika põhiülesanded Otsustusdiagrammid: BDD ja SSBDD Boole’i operatsioonid (SS)BDD-dega SSBDD-de omadused Kõrgtaseme otsustusdiagrammid (DD-d) –register-edastuste tase –käsusüsteemi tase Mitmedimensionaalsed otsustusdiagrammid Otsustusdiagrammide digitaalsüsteemide diagnostika

3. Technical University Tallinn ESTONIA 3 Introduction – Test Tools Test System Fault table System model Test generation Fault simulation Test result Fault diagnosis Go/No go Located defect Test experiment Test tools

4. Technical University Tallinn ESTONIA 4 Introduction – Test Tasks Fault Diagnosis and Test Generation as direct and reverse mathematical tasks: dy = F(x 1,..., x n )  F(x 1  dx 1,..., x n  dx n ) dy = F(X, dX) Direct task: Test generation: dX, dy = 1 given, X = ? Reverse task: Fault diagnosis: X, dy given, dX = ? Fault simulation: X, dy = 1 given, dx k = ? Fault Simulation is a special case of fault diagnosis

5. Technical University Tallinn ESTONIA 5 Binary Decision Diagrams 1959 - Lee C.Y. - Description of BF by graph-like structures 1967 - Ehrenfeucht A., Orlowska E - Fast evaluation of BE 1971 - Schneider B.N. - Representing BF by graphs (Abstract) > AG 1974 - Dipl. Thesis, TTU (Vaher/Ubar) - Fast evaluation of BE 1975 - Breitbart Y, Reiter A. - Fast evaluation of BE (Compiler design) 1976 - Ubar R. - Test generation > AG 1976 - Kuzmin V.A. - Complexity evaluation of BF by BP 1977 - Kuznetsov O.P. - Realization of BF by programmes 1977 - Akers S.B. - Test generation, introduced the name BDD 1981 - Thayse A. - BDDs in other fields: CAD, program optimization, AI 1986 - Bryant R.E. - manipulation of BDDs 1990 - Bryant R.A. - the first BDD package

6. Technical University Tallinn ESTONIA 6 Binary Decision Diagrams x1x1 x2x2 y x3x3 x4x4 x5x5 x6x6 x7x7 0 1 Simulation: 0 1 1 0 1 0 0 Boolean derivative: 1 0 Functional BDD

7. Technical University Tallinn ESTONIA 7 Binary Decision Diagrams D C qc q’ D S C q BDDs for flip-flops R c q’ S R q’q’ R U D Flip-Flop RS Flip-Flop JK Flip-Flop S J q R c q’ S R q’q’ C K K J U - unknown value

8. Technical University Tallinn ESTONIA 8 Elementary BDDs Elementary BDDs: 1 x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 & x2x2 x3x3 y x1x1 x1x1 x2x2 x3x3 1 x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 + x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 yx2x2 x3x3 Adder NOR AND OR

9. Technical University Tallinn ESTONIA 9 Building a SSBDD for a Circuit 1 & & x1x1 x2x2 x3x3 x 21 x 22 y a b a b y a x1x1 x 21 b x 22 x3x3 a y x3x3 y x3x3 x1x1 x 21 DD-library: Superposition of DDs  Superposition of Boolean functions: Given circuit: Compare to SSBDD Structurally Synthesized BDDs: ba

10. Technical University Tallinn ESTONIA 10 Boolean Operations with BDDs AND-operation: 1 & & x1x1 x2x2 x3x3 x 21 x 22 y a b 1 & & x5x5 x6x6 x51x51 x52x52 c d x4x4 g e y = e  g x3x3 x1x1 x 21 x 22 x6x6 x4x4 x51x51 x52x52 y OR-operation: x3x3 x1x1 x 21 x 22 y x6x6 x4x4 x51x51 x52x52 y = e  g

11. Technical University Tallinn ESTONIA 11 Boolean Operations with BDDs Boolean function:Inverted function: Dual function:Inverted dual function: y = x 1 x 2  x 3 y = x 1 x 2  x 3 = (x 1  x 2 ) x 3 x1x1 x2x2 x3x3 y x1x1 x3x3 x2x2 y x1x1 x3x3 x2x2 y* y*= (x 1  x 2 ) x 3 y * = x 1 x 2  x 3 x1x1 x2x2 x3x3 y *

12. Technical University Tallinn ESTONIA 12 BDD and DNF/KNF Boolean function: y = x 1 x 2  x 3 (x 4  x 5 x 6 ) x1x1 x2x2 x3x3 x5x5 x6x6 x4x4 1 y x 3 x 5 x 6 = 1 x1x1 x2x2 x3x3 x5x5 x6x6 x4x4 y x 1 x 4 x 5 = 1 0 Each 1-path represents a term in the DNF, each 0-path represents a term in the KNF

13. Technical University Tallinn ESTONIA 13 Transformation Rules for SSBDDs Commutative law: y = x 1  x 2 = x 2  x 1 x1x1 x2x2 y x2x2 x1x1 y Idempotent law: Exchange of nodes: BOOLEAN ALGEBRASSBDD Node passing: x1x1 x1x1 y x1x1 x2x2 y y = x 1  x 1  x 2 = = x 1  x 2 x2x2 x1x1 = =

14. Technical University Tallinn ESTONIA 14 Transformation Rules for SSBDDs Absorption law: BOOLEAN ALGEBRASSBDD Node passing: x1x1 x1x1 yy y = x 1  x 1 x 2 = x 1 x2x2 x1x1 x1x1 x2x2 = Distributive law: x1x1 x1x1 y x3x3 = x2x2 x1x1 y x3x3 x2x2 x1x1 y = x 1 x 2  x 1 x 3 = = x 1 (x 2  x 3 )

15. Technical University Tallinn ESTONIA 15 Transformation Rules for SSBDDs Assotiative law: BOOLEAN ALGEBRASSBDD Superposition: x1x1 z y y = x 1  (x 2  x 3 ) = = (x 1  x 2 )  x 3 = x2x2 x3x3 z x1x1 y x2x2 x3x3 z x3x3 y x1x1 x2x2 z =

16. Technical University Tallinn ESTONIA 16 Transformation Rules for BDDs Change-over switching of nodes: x1x1 x3x3 y x2x2 x1x1 x2x2 y x3x3 = Joint use of subgraphs: x1x1 x2x2 y x3x3 = x2x2 x1x1 x2x2 y x3x3 Removing subgraphs: x1x1 x1x1 y x2x2 = x3x3 x1x1 y x2x2 x3x3 =

17. Technical University Tallinn ESTONIA 17 Representing by SSBDD a Circuit & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro 6 7373 1 2 5 7272 7171 y 0 1 y = c y e y = c y  e y = x 6,e,y x 73,e,y  d ey b ey y = x 6 x 73  ( x 1  x 2 x 71 ) ( x 5  x 72 ) Structurally synthesized BDD for a subcircuit (macro) To each node of the SSBDD a signal path in the circuit corresponds

18. Technical University Tallinn ESTONIA 18 SSBDDs vs. BDDs Advantages of SSBDDs compared to the BDDs: Complexity explosion is avoided –The number of nodes is linear with the circuit size (determined by the number of paths in macros) Test-specific structural features can be represented –Each node represent a signal path in the circuit –Faults of the circuit are directly represented in SSBDDs –Circuit’s dynamic (hazards, risk, delays) can be investigated with SSBDDs Processing speed can be increased due to special properties of SSBDDs –Test generation (search space can be reduced) –Fault simulation (the speed of fault analysis can be increased) –Fault diagnosis (minimization of experiments easily controlled) Disadvantage: SSBDDs cannot be minimized

19. Technical University Tallinn ESTONIA 19 SSBDDs vs. BDDs Increasing the Speed of Test Generation with SSBDDs NA B Theorem: In SSBDD there exists always a path between the two successors A and B of N, either from A to B or from B to A 1 23 4 5 9 6 78 11 10 0 1 Breake search here Task: Activate a path to 1 Property of SSBDD: Result: Tracing is forced in nodes 1,9,10  Output 0 Another trials possible from 2,3,4  Not needed

20. Technical University Tallinn ESTONIA 20 SSBDDs vs. BDDs Increasing the Speed of Fault Simulation with SSBDDs Theorem: If a path in SSBDD is activated by a test pattern to 0 (or 1), then no faults can be detected by this pattern at nodes left in the oposite direction 1 (or 0) & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro Example: 6 7373 1 2 5 7272 7171 y 1 The activated path is shown in bold The output value is 1 No need of fault simulation in nodes 6 and 1

21. Technical University Tallinn ESTONIA 21 SSBDDs vs. BDDs Increasing the Speed of Fault Location with SSBDDs Theorem: If a path in SSBDD is activated to 0 (or 1), and an error is observed on the output, then no faults at nodes left in oposite direction 1 (or 0) can be the causes of the error Error detected Error signal traced C Circuit under guided probing:... Where to continue pinpointing? SSBDD for the component C: 1 23 4 5 6 8 1 7 The activated path is shown in bold The output value is 0 Faults can be detected only in nodes 1,6,7

22. Technical University Tallinn ESTONIA 22 SSBDDs vs. Gate-Level Models Advantages of SSBDDs compared to the Gate-Level Models: Complexity reduction –Faults domain: each node represent all the faults of the corresponding signal path (fault collapsing) –Time domain: each node represent the delay of the corresponding signal path Hierarchical approaches are easy –SSBDD for a subcircuit can be represented as a macro –No special manipulation procedures for different macros are needed –No model libraries for different tools are needed

23. Technical University Tallinn ESTONIA 23 Extentions of BDDs 1980 - Multi-Terminal DDs for uncertainty in sequential circuits (1993) –Automatika I Telemehanika, No5, 1980 1981 - Word-Level DDs for Data-Paths –Nachrichtentechnik-Elektronik 31 (1981, H.1) 1983 - DDs with multi-output internal nodes –Proceedings of TTU No. 550 1983 - Vector DDs for output behaviour of microprocessors –Fault-Tolerant Computing Symposium, Milano Recent papers on high-level DDs: R.Ubar. Test Synthesis with Alternative Graphs. J.of IEEE Design and Test of Computers. Spring, 1996, pp.48-59 R.Ubar. Combining Functional and Structural Approaches in Test Generation for Digital Systems. J. of Microelectronics and Reliability, Elsevier Science Ltd. Vol. 38, pp.317-329, 1998 J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. of Electronic Testing. Kluwer Acad. Publ. Vol. 16, No. 3, pp. 213-226, 2000. R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with DDs. IEEE ISCAS’2000 Conf., Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.

24. Technical University Tallinn ESTONIA 24 Generalization of MTBDDs for FSMs 1/0 3/0 5/0 6/1 4/1 2/1 x1 x2 x1 Res q’ x1 3.0 x2 4.1 5.0 6.1 x1 1.0 *.0 q.y 1 1 1 2 3 4 5 6 * 3 4 2.1 5 6 8 9 10 12 11 13 7 1.0 2 0 0 0 1 1 1 State Transition Diagram: New features: representing vectors multi-output internal nodes multi-terminal BDDs

25. Technical University Tallinn ESTONIA 25 High-Level Decision Diagrams y 4 y 3 y 1 R 1 + R 2 IN + R 2 R 1 * R 2 IN* R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Superposition of High-Level DDs: A single DD for a subcircuit R2R2 R 2 + M 3 Instead of simulating all the components in the circuit, only a single path in the DD should be traced M1M1 M2M2

26. Technical University Tallinn ESTONIA 26 Faults and High-Level Decision Diagrams RTL-statement: Terminal nodes RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults K: ( If T,C) R D  F(R S1,R S2,…R Sm ),  N

27. Technical University Tallinn ESTONIA 27 High-Level Decision Diagrams Register-Level Data Path:

28. Technical University Tallinn ESTONIA 28 High-Level Decision Diagrams Representing transparency functions in Decision Diagrams

29. Technical University Tallinn ESTONIA 29 DD Synthesis from Behavioral Descriptions BEGIN Memory state: M Processor state: PC, AC, AX Internal state:TMP Instruction format:IR = OP. A. F0. F1. F2. Execution process: EXEC: BEGIN DECODE OP  ( 0: AC  AC + M  A  1: M[A]  AC, AC  0 2: M[A]  M[A]+ 1, IF M[A]= 0 THEN PC  PC + 1 3: PC  A...................................... 7: IF F0 THEN AC  AC + 1 IF F1 THEN IF AC = 0 THEN PC  PC + 1 IF F2 THEN (TMP  AC, AC  AX, AX  TM’) END Procedural description of a microprocessor

30. Technical University Tallinn ESTONIA 30 DD Synthesis from Behavioral Descriptions Start AC = AC + M [A] AC = AC + 1 PC = A M [A] = AC, AC = 0 M [A] = M [A] + 1 PC = PC + 1 1 2 3 4 6 5 AC = AX, AX = AC 7 PC = PC + 1 AC = AX, AX = AC 8 9 10 11 OP=0 OP=1 OP=2 OP=3... OP=7 M[A]=0 M[A]=1 F0=1 F0=0 F1=1 F1=0 F2=0 F2=1 AC=0 AC  0 F2=1 F2=0F2=1 F2=0 Symbolic execution tree:

31. Technical University Tallinn ESTONIA 31 DD Synthesis from Behavioral Descriptions Generation of nonprocedural descriptions via symbolic execution Terminal contexts

32. Technical University Tallinn ESTONIA 32 DD Synthesis from Behavioral Descriptions Decision Diagram for AC OP AC AC+M [A] #0 F0F2 AC AX AC+1 0 1 2,3 7 0 0 1 1

33. Technical University Tallinn ESTONIA 33 High-Level Decision Diagrams A B C M ADR MUX 1 2 CC CON D Control Path Data Path  / FF y x q q z z 1 z 2 Digital system: DD-model for a digital system:

34. Technical University Tallinn ESTONIA 34 High-Level Decision Diagrams Digital system: DD-model for a digital system:

35. Technical University Tallinn ESTONIA 35 Test Generation for Processors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  A I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A High-Level DDs for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

36. Technical University Tallinn ESTONIA 36 Test Generation for Processors High-Level DD-based structure of the microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: OUT R A IN I

37. Technical University Tallinn ESTONIA 37 Test Generation for Processors IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load

38. Technical University Tallinn ESTONIA 38 Test Generation for Processors IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 I IN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Conformity test program for decoder: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data generation: Data IN,A,R are generated so that the values of all functions were different

39. Technical University Tallinn ESTONIA 39 Vector Decision Diagrams 3,4 0 2 q 1 0 1 0 q  1  4 x A  2 1  5 x B  3 A 0 1 0 q x A B + C  A + 1 1 3 x C  C + B 0 4 x A A + C B 0 4 1 q x A B + C  B C 14 2 q x A 1 0 x B A + B  C 0 x C x A 1 x C 3 0 M=A.B.C.q Vector Decision Diagrams: 1 1 q x A 0 q A i B’ + C’ #1 q B i B’ + C’ #2 0 q A i  A’ + 1 #4 2 1 x B q C i  C’ #3 0 q C i A’ + B’ #5 3 1 x C q A i B’ +  C’ #5 0 q C i A’ + B’ #5 4 1 x C q C i  C’ #5 0 B A i A’ + B’+C’ x A 0 q #5  B’ q B i  #5 Concurrent simulation in space: j – adressing variable

40. Technical University Tallinn ESTONIA 40 Two-Dimensional Decision Diagrams I 1 I 3 t i 1 i 1 PC + 1 PC + 2 0 1 2 3 AB A 1 A 2 OUT = AB.DB (t) t 0, 2 i 1 PC + 1 PC + 2 2 DB AB I 2 2 t 1, 3 i 1 2 AB t 4 i 1 L INP 4 DB AB A 1 A 2 2 3 i 1 INP + 1 5 DB AB H Instruction: SHLD I 1.I 2 3 = 0.4.2 (DB(t=3).DB(t=2))  L ((DB(t=3).DB(t=2)) + 1)  H I 1 I 2 I 3 012457 DDs for representing microprocessor output behaviour i 2 DB(t=2) DB(t=3) L H INP (H,L) Concurrent simulation: in space: i – adressing variable in time: t – adressing variable i t space time