1. Digitaalsüsteemide verifitseerimise kursus1 Formal verification: BDD BDDs applied in equivalence checking

2. Digitaalsüsteemide verifitseerimise kursus2 Equivalence Checking Two principal approaches: Transform implementation and spec ( reference implementation) to a canonical form Search for an input assignment that would distinguish the responses of the implementation and reference implementation. BDD-s applied for canonical form

3. Digitaalsüsteemide verifitseerimise kursus3 Canonical forms of Boolean functions Minimized function. Karnaugh map! Full normal form Truth table  These forms are not compact!

4. Digitaalsüsteemide verifitseerimise kursus4 Decision Diagrams and Equivalence Theoretically, any canonical form has exponential worst case complexity. Luckily for many practical functions compact BDDs exist. We will cover the topic of utilizing BDDs in equivalence checking and symbolic simulation.

5. Digitaalsüsteemide verifitseerimise kursus5 Examples of canonical forms Is f. ¬ac + b¬c + a¬b equivalent to f. a¬c + ¬bc + ¬ab ? c ab 00011110 0111 1111

6. Digitaalsüsteemide verifitseerimise kursus6 Is f. ¬ac + b¬c + a¬b equivalent to f. a¬c + ¬bc + ¬ab ? c ab 00011110 0111 1111 Examples of canonical forms

7. Digitaalsüsteemide verifitseerimise kursus7 Overview of the history of BDDs 1959Lee, BDD first mentioned 1976Ubar, alternative graphs aka structural BDD-s 1978Akers, BDD protagonist 1985Bryant, ROBDD ROBDD-s started a big BDD boom

8. Digitaalsüsteemide verifitseerimise kursus8 Binary Decision Diagrams BDD is a directed acyclic graph with a single root node and two terminal nodes: 0-node and 1-node Each internal node is labeled by a Boolean variable. From each internal node, two edges will originate which correspond to 0 and 1 value of the variable.

9. Digitaalsüsteemide verifitseerimise kursus9 Binary Decision Diagrams BDD for Boolean function (x1·x2) V x3 BDD is generated by Shannon expansion:

10. Digitaalsüsteemide verifitseerimise kursus10 BDD generation example Shannon’s expansion: f=ab+bc b+bcbc cc a) Generate a decision treeb) Reduced BDD

11. Digitaalsüsteemide verifitseerimise kursus11 Interpretation of BDDs By traversing the paths of a BDD: 1.Calculate the value of f. 2.Derive the function f=ab+a¬bc+¬abc+¬a¬bd

12. Digitaalsüsteemide verifitseerimise kursus12 Ordered BDD (OBDD) Boolean variables occur in a concrete order along the paths of the BDD No path has more than 2 occurrences of the same variable.

13. Digitaalsüsteemide verifitseerimise kursus13 Reduced OBDD (ROBDD) Rules of reduction: a) Node removalb) Node sharing

14. Digitaalsüsteemide verifitseerimise kursus14 Reduction example

15. Digitaalsüsteemide verifitseerimise kursus15 ROBDD properties +ROBDD is a canonical representation of a Boolean function Equivalence of Boolean functions is checked by isomorphicity of their respective BDDs –ROBDD worst case memory consumption is exponential Not applicable in many practical cases (E.g. multiplier!)

16. Digitaalsüsteemide verifitseerimise kursus16 BDD size depending on the ordering f = ab + a¬bc + ¬abc + ¬a¬bd

17. Digitaalsüsteemide verifitseerimise kursus17 BDD size depending on the ordering There are functions whose BDD size grows linearly wrt number of variables There are functions whose BDD size grows exponentially in the worst case wrt number of variables There are functions whose BDD size grows ALWAYS exponentially, regardless of the ordering (E.g. multiplication!)

18. Digitaalsüsteemide verifitseerimise kursus18 BDD size depending on the ordering Finding an optimal ordering for the variables is an unsolved problem Various heuristics applied

19. Digitaalsüsteemide verifitseerimise kursus19 Dynamic reordering of BDD nodes

20. Digitaalsüsteemide verifitseerimise kursus20 Structural BDD-s (Ubar’76) Definition similar to the one of BDD SSBDD is generated in a recursive manner, substituting logical gates by elementary BDDs

21. Digitaalsüsteemide verifitseerimise kursus21 Structural BDD-s (Ubar’76) ROBDD generated for each output of the circuit SBDD generated for each fanout-free (tree- like) subcircuit  required memory linear!

22. Digitaalsüsteemide verifitseerimise kursus22 SBDD properties Different of ROBDD-s, SBDDs are planar Nodes labeled by variables and inverted variables; concept of 0 and 1 direction!

23. Digitaalsüsteemide verifitseerimise kursus23 Alternative notation Moving to the right (downwards) from a node corresponds to variable value 1 (value 0). Exiting to the right (downwards) from the graph corresponds to function value 1 (value 0). Terminal nodes not shown!

24. Digitaalsüsteemide verifitseerimise kursus24 Circuit, its BDD and SBDD

25. Digitaalsüsteemide verifitseerimise kursus25 SBDD generation

26. Digitaalsüsteemide verifitseerimise kursus26 Structural paths BDD nodes 1:1 correspondence between SBDD nodes and structural paths in the fanout-free circuit => säilib info skeemi struktuuri kohta!

27. Digitaalsüsteemide verifitseerimise kursus27 ROBDD vs SBDD

28. Digitaalsüsteemide verifitseerimise kursus28 SBDD summary SBDD model has a number of advantageous properties for modeling logic circuits: 1) Preserve structural information 2) Suitable for fault modeling and simulation 3) Linear memory requirements