Presentation on theme: "CHAPTER 16 – CONTROL UNIT OPERATION"— Presentation transcript:
1 CHAPTER 16 – CONTROL UNIT OPERATION Andrae DarbyBrian McCaulCarlos EstradaCristina RodriguezYuniel Barbon
2 CONTROL UNITThe Control Unit can be thought of as the brain of the CPU itself. It controls based on the instructions it decodes, how other parts of the CPU and in turn, rest of the computer systems should work in order that the instruction gets executed in a correct manner.AADAD
3 MICRO OPERATION (micro-ops or μops) A computer executes a programInstruction cycle: made up of smaller units: fetch, indirect, execute and interrupt with only the fetch & execute cycles always being used.Each cycle has a number of stepssee pipeliningCalled micro-operationsEach step is very simpleAccomplishes very littleA
4 MICRO OPERATION (micro-ops or μops) Micro operations are the functional, or atomic operations of a processor.A
6 Fetch cycleThe fetch cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory. The four registers used are:Memory Address Register (MAR)Connected to address lines of the system busSpecifies address in memory for read or write opsMemory Buffer Register (MBR)Connected to data lines of the system busContains last value to be stored inor read from memoryProgram Counter (PC)Holds the address of next instruction to be fetchedInstruction Register (IR)Holds the last instruction fetchedAAD
7 Fetch Sequence A Address of next instruction is in PC Address (MAR) is placed on address busControl unit issues READ commandResult (data from memory) appears on data busData from data bus copied into MBRPC incremented by 1 (in parallel with data fetch from memory)Data (instruction) moved from MBR to IRMBR is now free for further data fetchesA
8 Fetch Sequence A t1: MAR <- (PC) t2: MBR <- (memory) PC <- (PC) +It3: IR <- (MBR)(tx = time unit/clock cycle) ort3: PC <- (PC) +1IR <- (MBR)A
9 Rules for Grouping Micro Operations Proper sequence must be followedMAR <- (PC) must precede MBR <- (memory)Conflicts must be avoidedMust not read & write from the same register in one time unit.For example: MBR <- (memory) & IR <- (MBR) must not be in same cycleAlso: PC <- (PC) +I involves addition. To avoid duplication of circuitry.Use ALU to perform this additionThe use of the ALU may use additional micro-operationsA
10 Questions What is the control unit? Which instruction cycle is always used?
11 The Indirect CycleHappens after the fetch cycle, and fetches source operandsStep 1: MAR (IR(Address))Address field of the instruction to Memory Address RegisterStep 2: MBR MemoryFetches the address of the operand and places in MBRStep 3: IR(Address) (MBR(Address))Direct address from MBR to Instruction RegisterThe IR is now in the same state as if indirect addressing had not been usedBM
12 The Interrupt CycleHappens when a test determines an enabled interrupt has occurred after the execute cycle.Step 1: MBR (PC)Move Program Counter contents to Memory Buffer RegisterStep 2: MAR Save_Address PC Routine_AddressSaved address of the stored PC to Memory Address Register and address of new interrupt routine to Program CounterStep 3: Memory (MBR)Move Memory Buffer Register contents to MemoryThis is the minimum and may require additional micro-operationsBM
13 The Execute Cycle (ADD) There is a different sequence of micro operations for each op code.Example: An Add InstructionADD R1, X (This adds contents of X to R1)Might proceed like so:Step 1: MAR (IR(Address))Step 2: MBR MemoryStep 3: R1 (R1) + (MBR)BM
14 The Execute Cycle (ISZ) ISZ XIncrements the location of X by 1 and if the result if zero then the next instruction is skipped.Step 1: MAR (IR(Address))Step 2: MBR MemoryStep 3: MBR (MBR) + 1Step 4: Memory (MBR)If ((MBR) = 0 ) then (PC (PC) + I )BM
15 The Execute Cycle (BSA) BSA XBranch and Save address instructionAddress of instruction following BSA instruction is saved in X and execution continues at location X+1. X will later be used for returnStep 1: MAR (IR(Address)) MBR (PC)Step 2: PC (IR(Address)) Memory (MBR)Step 3: PC (PC) + IBM
16 The Instruction CycleEach Phase of the Instruction Cycle can be decomposed into a sequence of elementary micro-operationsEx: one sequence each for fetch, indirect, interrupt, and in the execute cycle, one sequence per op code.We need to tie sequences of micro-operations together, and we so this by assuming a new 2-bit register, the Instruction Cycle Code (ICC). It designates the state of the processor by the cycle it is in as follows:00:Fetch01:Indirect10:Execute11:InterruptBM
17 The Instruction Cycle (Cont.) The following flowchart shows the sequence of micro-operationsBM
18 Questions How many bits is the ICC register? Does the sequence of micro-operations on the execute cycle depend on the opcode?
20 Characterization of the control unit Define the basic elements of the processor.Describe the micro-operations that the processor performs.Determines the function that the control unit must perform to cause the micro-operations to be performed.CE
21 Basic elements of processor: ALU (functional essence of the computer)Registers (Store data internal to the processor. Contain info needed to manage instruction sequencing. Contain data that go or come from the ALU, memory, and I/O modules)Internal data paths (move data between registers and between ALU)Internal data paths (Link registers to memory and I/O modules by means of a bus)Control unit (Causes operations to happen within the processor)CE
22 Sequence of micro-operations Transfer data from one register to anotherTransfer data from a register to an external interfaceTransfer data from an external interface to a registerPerform an arithmetic or logic operation, using registers for input and outputCE
23 Control Unit Functions Sequencing: control unit causes the processor to step through a series of micro-operations in sequence, based on the program being executedExecution: control unit causes each micro-operation to be performedCE
25 Control Unit InputsClock: control unit causes one micro-operation (or set of simultaneous micro-operations)Instruction register: opcode of the current instruction is used to determine which micro-operations to perform during the execute cycleFlags: needed by the control unit to determine the status of the processor and the outcome of previous ALU operationsControl signals from control bus: Provides signals to the control unit (interrupt, acknowledgement)CE
26 Control Unit OutputsControl signal within the processor: (type 1): cause data to be moved from one register to another (type 2): activate ALU function.Control signals to control bus: (type 1): control signals to memory. (type 2): control signals to the I/O modules.CE
27 Control Unit and the Fetch Cycle MAR <- (PC)control unit activates the control signal that opens the gates between the bits of the PC and the bits of the MAR.MBR <- (memory)control signal opens gates, allowing MAR contents onto busmemory read signal to buscontents of data bus stored in MBRsignal to logic that increment PC and store the result back to PCCE
29 Questions The control unit performs which 2 basic tasks? What is sequencing and execution?
30 Internal Processor Organization Usually a single internal busGates control movement of data onto and off the busControl signals control data transfer to and from external systems busTemporary registers needed for proper operation of ALUCRAD
31 CPU with Internal BusNOTE: A single internal bus connects the ALU and all the processor registersCRAD
32 Internal Processor Organization Movement of data onto and off the bus from each is register possible through gates and control signalsNew registers: Y and ZAid in operation of ALUSource for additional operands; temporary storage (Y input storage; Z output storage)ALU: combinational circuit (output is a pure function of the present input only)Control signals activate ALU function input is transformed to output (register Z is the temporary output; ALU output is NOT connected directly to BUS)CR
33 Intel 8085 Other components in this processor: Incrementer/decrementer address latch avoids use of ALU for incrementing SP or PCInterrupt control handles interrupt signalsSerial I/O control interfaces to devicesCRAD
35 Intel 8085 Pin Configuration External signals into and out of the 8085 are linked to the external system bus. These signals interface the processor and the rest of the system.CRAD
36 External Signals Memory and I/O Initiated Symbols HoldHeld Acknowledge (HOLDA)READYInterrupt-Related SignalsTRAPInterrupt Request (INTR)Interrupt AcknowledgeCPU InitializationRESET INREST OUTVoltage and GroundAddress and Data SignalsHigh Address (A15-A8)Address/Data (AD7-AD0)Serial Input Data (SID)Serial Output Data (SOD)Timing and Control SignalsCLK (OUT)X1, X2Address Latch Enable (ALE)Status (S0, S1)IO/MRead Control (RD)Write Control (WR)CR
38 8085 TimingThe timing of processor operations is synchronized by the clock and controlled by the control unit with control signals.Timing diagram shows the value of external control signals. Three machine cycles (3-5 states per machine cycle) are shown.The Address Latch Enable (ALE) signals the start of each machine cycle from the control unit.Must give enough time for signal level to stabilize.CR
39 Questions What are the temporary registers which aid in ALU operation? What controls data transfer to and from external bus?
40 First Programmable Computer Z1 began development in 1936 by Germany’s Konrad ZuseConsidered the first electrical binary programmable computer64-word memory (each word contained 22 bits), a total of 176 bytes memory and a clock speed of 1 HzProgram through punch tape/output through punch tapeYB
42 Beginning of Binary Operations George Boole wanting a rapid development in electrical technology discovered logic functionsAt that time all operations were done by opening and closing a switchHe realized that a combination of switches can bring out a new world of logical operations which he called binary logicBoole also arrived to Boolean Algebra to solve this operationsYB
46 Hardwired Implementation (1) Control Unit Key Inputs are: instruction register, the clock, flags, and control bus signalFlags and control bus are directly useful to the CUEach bit means somethingInstruction registerProvides Op-code’s that the CU uses for instructions for actionsCU logic simplified by decoder which takes an encode signal and produces a single outputYBAD
47 Hardwired Implementation (2) ClockRepetitive sequence of pulsesUseful for measuring duration of micro-opsMust be long enough to allow signal propagationDifferent control signals at different times within instruction cycleNeed a counter with different control signals for t1, t2 etc.YBAD
49 Control Unit LogicProcessor’s use Boolean equations to define the control unitControl Unit controls the state of instruction cycleControls the timing generator to reset at the end of each subcycleSubcycleFetchIndirectExecuteInterruptYB
50 Example of Boolean Equations Consider the following interpretationPQ = 00 Fetch CyclePQ = 01 Indirect CyclePQ = 10 Execute CyclePQ = 11 Interrupt CycleThen if this expression defines C5:C5 = P*Q*T2 + P*q*T2This means that the control signal C5 will be asserted during the second time unit of both the fetch and indirect cyclesYB
51 Problems With Hard Wired Designs Complex sequencing & micro-operation logicDifficult to design and testInflexible designDifficult to add new instructionsYBAD
52 Questions What are the 4 subcycles of a control unit? What are the 4 key inputs of a control unit?
53 Additional Information Intel 8080:Processor Organization:omputer.organization/02.comp.org.htmlphp
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