C166 Family-High Performance 16-Bit Microcontrollers

C166 Family-High Performance 16-Bit Microcontrollers
SAB-C167CR SAB 8xC166 C167x C165 C163 C164x C161x XRAM 1KByte XRAM 1KByte RAM 1KByte CAN BUS- CONTROL RAM 1KByte CORE ROM PWM INTERRUPT UNIT IR+PEC- CONTROL CAPCOM 1+2 SSC USART WDT ADC GPT 1+2 The Reference Class 1

C166 Family The Three Subsystems
WDT OSC. PEC CPU ROM / RAM PORTS CAPCOM ADC Bus Ext.. Processor -System Interrupt-System USART GPTs Peripheral-System Flash Control X-Bus Sync Communication PWM Peripheral. The Reference Class 1

C166 Family The Best of Both Worlds
WDT OSC. PEC CPU ROM / RAM PORTS CAPCOM ADC Bus Ext.. Processor -System Interrupt-System USART GPTs Peripheral-System Flash Control X-Bus Sync Communication PWM Periphrl. Microcontrollers: Control oriented instruction set optimized event handling “System on Silicon” Microprocessors: High computational power high data throughput good addressing capabilities HLL-supporting architecture The Reference Class 1

The Modular Concept The Reference Class CPU Processor Downgraded Core
n x 4 KB ROM n x 512 B RAM Internal CPU Internal ROM RAM n x 8 KB Flash-EPROM OSC. Interrupt Controller PEC WDT Ext.. 10-bit Bus ADC USARTs GPTs CAPCOM Control PORTS Different Mix + CAN More I/O More AD-Ch. + PWM The Reference Class 1

Four Bus Modular System
X Bus Modules XRAM SSP New Modules CAN I²C ROM 8K 32K Flash 128K New Modules OTP 64K 16 - b i t RAM 1k New Modules 32 bit Core 2x16 bit New Modules 16 - b i t Timers USART SSC Ports New Modules WDT ADC CAPCOM Basic Library Modules The Reference Class 1

Roadmap C167CR C167SR C167S C167 C164 8xC166 Highly Integrated
* 16 M Address Range * 2/4 KByte RAM * 32 CAPCOM * 4 PWM * 2 Serial Interface * 5 Timer * Chip Selects Benefits in System Integration * Extensive I/O C167CR * CAN * 4K RAM * PLL C167SR * 2KB RAM * PLL C167S * 32K ROM * 2KB RAM * PLL * 2KB RAM C167 General Purpose Balanced Peripheral set for a broad Application Ranges: Price differentiation: * 1K / 2 KB RAM * ROM / Flash / OTP * CAPCOM * PWM * Serial Interfaces * Timer * 10-bit / 8bit ADC * full Bus Support/ MUX Bus only C164 8xC166 * 2KB RAM * 64KB OTP/ROM/Flash * Full-CAN 2.0B active * Power Management / RTC * CAPCOM6 * P-MQFP-80 * 1KB RAM * 32KB ROM * 32KB Flash * P-MQFP-100 Low Cost Processor Oriented C165 C163 * different RAM Size * up to 16 M Addr. Range * up to 5 Timers * Serial Interfaces SSP, SSC * less Chip Selects * full Bus Support/ MUX Bus only * 3 V Options * 25 MHz Option C161x * 2KB RAM * 3V * P-TQFP-100 * 1KB RAM * SSP * 3V * reduced Peripherals * P-TQFP-100 * 16MHz CPU * 4 M address * 1-2KB RAM * Pwr. Man. / RTC * P-MQFP-80/100 Roadmap 2

Numbering Scheme 8xC166 Products
Prefix Memory Type Memory Package Temp. Range Type Code Designation Size Code Code Code (-) T3 0° / 70° (-) ROMLess M C166 C166W -40° / 85° 80 (-) T3 T4 0° / 70° -40° / 85° -40° / 110° Metal Mask ROM C166 C166W 5 M (-) T3 0° / 70° SAB 83 -40° / 85° (-) T3 T4 0° / 70° -40° / 85° 32KBytes -40° / 110° 5 M (-) 0° / 70° C166 C166W 88 0° / 70° Flash EEPROM W = without prescaler M = Metric Quad Flatpack (-) no suffix Overview 3

Numbering Scheme C161/C163/165 Products
Prefix Temp. Range Type Memory Code CPU Package Code Designation Size Type Freq Code B C161V / K / O* L 16 M (-) B (-) L (-) F B,F C163 (-) L 25 F SA B,F 16 F 25 F 128kB FLASH B,F C165 R L (-) 25 M,F * difference later on in this Foilset 4KB Metal Mask ROM B = 0/ 70 °C F = -40/ 85 °C M = Metric Quad Flatpack F = Thin Quad Flatpack L = ROMless R = MASK ROM F = FLASH (-) = 0kB 16 = 128kB Overview 3

Numbering Scheme C164 Products
Prefix Temp. Range Type Memory Code CPU Package Code Designation Size Type Freq Code (-) L (-) M,F SA B,F,H,K C164CI 8 E (-) M,F 8 R (-) M,F 64KB OTP B = 0/ 70 °C F = -40/ 85 °C H = -40/ 110°C K = -40/ 125°C M = Metric Quad Flatpack F = Thin Quad Flatpack L = ROMless R = MASK ROM E = EPROM (-) = 0kB 8 = 64kB Overview 3

Numbering Scheme C167 Products
Prefix Temp. Range Type Memory Code Package Code Designation Size Type Code B,F C167 (-) L M ROMLess B C167S 4 R M Mask ROM B,F,K C167SR (-) L M 32KBytes SA B, F, K C167CR 4* R* M (-) L M Flash B C167CR 16* F M 128KBytes B, F,K C167CR 16* R* M B= 0/ 70 °C F= -40/ 85 °C K= -40/110 °C C= CAN Interface R= 2KBytes XRAM M= Metric Quad Flatpack Overview 3

Overview - C161V Block Diagram
C166-Core 16 Data no RAM CPU Dual Port Instr./Data Data 1 KByte ROM 32 16 OSC input: 16MHz; prescaler or direct drive XTAL PEC External Instr./Data Watchdog Interrupt Controller Peripheral X-Bus no 5 ext. IR Interrupt Bus 16 Peripheral Data 16 XBUS (16-bit NON MUX Data / Addresses) GPT1 USART Sync. Channel Port 6 External Bus, MUX only XBUS Control, no CS Logic, (SPI) T2 4 T3 ASC SSC Port 0 T4 BRG BRG 16 Port 4 Port 1 Port 5 Port 3 Port 2 6 16 2 12 7 Overview - C161V Block Diagram 3

Overview - C161K Block Diagram
C166-Core 16 Data no RAM CPU Dual Port Instr./Data Data 1 KByte ROM 32 16 OSC (input: 16MHz; prescaler or direct drive) XTAL PEC External Instr./Data Watchdog Interrupt Controller Peripheral X-Bus no 5 ext. IR Interrupt Bus 16 16 Peripheral Data XBUS (16-bit NON MUX Data / Addresses) GPT1 USART Sync. Channel Port 6 External Bus, XBUS Control, 2 x CS Logic (SPI) T2 4 T3 ASC SSC Port 0 T4 BRG BRG 16 Port 4 Port 1 Port 5 Port 3 Port 2 6 16 2 12 7 Overview - C161K Block Diagram 3

Overview - C161O Block Diagram
C166-Core 16 Data no RAM CPU Dual Port Instr./Data Data 2 KByte ROM 32 16 OSC (input: 16MHz; prescaler or direct drive) XTAL PEC External Instr./Data Watchdog Interrupt Controller Peripheral X-Bus no 11 ext. IR Interrupt Bus 16 16 Peripheral Data XBUS (16-bit NON MUX Data / Addresses) GPT1 GPT2 USART Sync. Channel Port 6 External Bus, XBUS Control, 4 x CS Logic (SPI) T2 4 T3 T5 ASC SSC Port 0 T4 T6 BRG BRG 16 Port 4 Port 1 Port 5 Port 3 Port 2 6 16 2 12 7 Overview - C161O Block Diagram 3

Overview - C161RI Block Diagram
C166-Core 16 RAM 1 KByte Data no Dual Port Instr./Data CPU Data ROM 32 16 OSC (input: 16MHz; prescaler or direct drive) XTAL Watchdog PEC External Instr./Data RTC I2C-Bus Interrupt Controller 11 ext. IR Interrupt Bus 16 XRAM 2 KByte 16 Peripheral Data XBUS (16-bit NON MUX Data / Addresses) 8-bit ADC USART Sync. Channel GPT1 GPT2 Port 6 External Bus, XBUS Control, 5 x CS Logic (SPI) T2 T5 8 4 Channels ASC SSC T3 T6 Port 0 BRG BRG T4 16 Port 4 Port 1 Port 5 Port 3 Port 2 7 16 6 15 8 Overview - C161RI Block Diagram 3

Overview - C163 Block Diagram
1 KByte PLL progr. multiplier (W/0.5/1.5/2/../5) SSP Module 12.5 Mbit/s Port 6 Port 0 Port 4 Port 1 Port 5 Port 3 CPU Dual Port Interrupt Controller Watchdog Peripheral Data External Instr./Data USART ASC BRG GPT1 T3 T4 GPT2 T2 T5 T6 16 6 8 32 PEC up to 128 KByte Flash EPROM Interrupt Bus Data Port 2 Instr./Data XBUS (16-bit NON MUX Data / Addresses) External Bus, XBUS Control, 5 * CS Logic 11 ext. IR C166-Core XTAL RAM 1 KByte Overview - C163 Block Diagram 3

Overview - C164CI Block Diagram
C166-Core 16 64 K ROM (C164 Cl-8-RM) or OTP C164-8EM) Data Dual Port RAM Instr./Data CPU Data 2 KByte 32 16 PLL-Oscillator prog. Multiplier: 0.5; 1; 1.5; 2; 2.5; 3; 4; 5 Watchdog PEC External Instr./Data P4.5/ CAN RxD P 4.6/ CAN TxD Interrupt Controller 13 ext. IR RTC Full-CAN Interface V2.0B active Interrupt Bus 16 16 Peripheral Data XBUS (16-bit NON MUX Data / Addresses) 10-Bit ADC USART Sync. Channel GPT1 CAPCOM 2 CAPCOM6 Unit for PWM Generation External Bus, (8/16 bit; MUX only & XBUS Control 16 (SPI) T2 Port 0 8-Channels 8-Channel ASC SSC T3 Timer 13 BRG BRG Timer 7 Timer 8 T4 1 Comp. Channel 3/6 CAPCOM Channels Port 4 Port 5 Port 3 Port 8 Port 1 6 8 9 4 16 Overview - C164CI Block Diagram 3 1 1 1

XBUS (16-bit NON MUX Data / Addresses)
C166-Core 16 RAM 2 KByte no Data CPU Dual Port Instr./Data Data ROM 32 16 XTAL OSC CPU clock: 20 / 25 MHz PEC External Instr./Data Watchdog Peripheral X-Bus Interrupt Controller 12 ext. IR Interrupt Bus 16 16 Peripheral Data XBUS (16-bit NON MUX Data / Addresses) GPT1 GPT2 USART Sync.Channel (SPI) Port 6 External Bus, XBUS Control, 5 * CS Logic T2 8 T3 T5 ASC SSC Port 0 T4 T6 BRG BRG 16 Port 4 Port 1 Port 5 Port 3 Port 2 8 16 6 16 8 Overview - C165 Block Diagram 3

Overview - SAB 80C166 Block Diagram
up to Data 32 KByte RAM SAB 8xC166 CPU CORE Dual Port ROM/ Instr./Data Data 1 KByte Flash- 32 16 EPROM OSC XTAL PEC External Instr./Data Watchdog Interrupt Controller 19 ext. IR 16 Interrupt Bus Peripheral Data 16 10-Bit ADC USART USART GPT1 GPT2 CAPCOM External T2 Bus Timer 1 Timer 0 16 Channels ASC ASC T3 T5 Controller Port 0 BRG BRG T4 T6 16 Port 4 Port 1 Port 5 Port 3 Port 2 2 16 10 16 16 Overview - SAB 80C166 Block Diagram 3

Overview - C167 Block Diagram
C166-Core 16 EPROM ROM/ Flash up to 128 KByte RAM 2 KByte Data CPU Dual Port Instr./Data Data 32 16 PLL XTAL (input: 5 MHz) OSC (output: 20MHz) PEC External Instr./Data Watchdog Interrupt Controller 36 ext. IR 2KB XRAM Interrupt Bus 16 16 Peripheral Data XBUS (16-bit NON MUX Data / Addresses) Multi Funktional 10-Bit ADC USART Sync. Channel (SPI) GPT1 GPT2 CAPCOM1, 2 PWM Module Port 6 External Bus, XBUS Control, 5 * CS Logic T2 PT 1 8 Timer 1 16 Channels Timer 0 ASC SSC PT 2 T3 T5 32 Channels PT 3 Port 0 BRG BRG T4 T6 Timer 7 Timer 8 PT 4 16 Port 4 Port 1 Port 5 Port 3 Port 2 Port 8 Port 7 8 16 16 16 16 8 8 Overview - C167 Block Diagram 3

Overview - C167CR Block Diagram
C166-Core 16 128 KByte ROM/ EPRON FLASH Data RAM 2 KByte Dual Port CPU Instr./Data Data 32 16 PLL XTAL (input: 5 MHz) OSC (output: 20MHz) PEC External Instr./Data Watchdog CAN 2.0 B active Interrupt Controller 36 ext. IR Interrupt Bus 16 XBUS (16-bit NON MUX Data / Addresses) 2KB XRAM 16 Peripheral Data MultiFunktional 10-Bit ADC USART Sync. Channel (SPI) GPT1 GPT2 CAPCOM1, 2 PWM Module Port 6 External Bus, XBUS Control, 5 * CS Logic PT 1 T2 16 Channels Timer 1 Timer 0 8 PT 2 ASC SSC T3 T5 32 Channels PT 3 Port 0 BRG BRG T6 Timer 7 Timer 8 PT 4 T4 16 Port 4 Port 1 Port 5 Port 3 Port 2 Port 8 Port 7 8 16 16 15 16 8 8 Overview - C167CR Block Diagram 3

Overview (16 MHz) Complete 16-bit architecture with 32-bit bus to the internal ROM to process 8-bit, 16-bit and even 32-bit (MUL/DIV) operands 16 MHz CPU clock results in an instruction cycle time of 125ns which guarantees highest CPU performance To avoid an accumulator bottleneck 16 General Purpose Register (GPR) are implemented Up to 16 GPRs from a register bank Any register bank is freely locatable in internal RAM Easy and efficient programming is supported by powerful instructions combined with complex addressing modes Transparent programming of the on-chip peripherals via an universal Special Function Register (SFR) interface CPU 4

Block Diagram ROM / RAM interaction
On-Chip (EP)ROM CPU STK OV STK UV 4-Stage Pipeline Exec. Unit Instr. Ptr. Instr. Reg. MDL MDH SP STK OV STK UV On-Chip Static RAM 16 32 Mul./Div.-HW Bit-Mask Gen. ALU 16-bit Barrel-Shifter General R15 R0 Purpose Registers R15 R0 PSW SYSCON BUSCON 1 ADDRSEL 1 16 Context Ptr. Data Page Pointer Code Seg.Ptr CPU 4

Block Diagram ROM / RAM interaction
On-Chip (EP)ROM CPU STK OV STK UV 4-Stage Pipeline Exec. Unit Instr. Ptr. Instr. Reg. MDL MDH SP STK OV STK UV On-Chip Static RAM 16 Mul./Div.-HW Bit-Mask Gen. ALU 16-bit Barrel-Shifter 32 General R15 R0 Purpose Registers R15 R0 PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 16 Data Page Pointer Context Ptr. Code Seg.Ptr CPU 4

General Purpose Register (GPR)
Up to 16 GPRs = 1 Register bank Consisting of max. 8 Word-Registers 8 Word-Registers with lower and higher Byte access The GPRs are bit-addressable Any Register bank can be freely allocated in internal RAM The location of the active Register bank is determined by Context Pointer (CP) CP can be easily switched, to select another Register bank SWTC (one instruction cycle) CPU 4

Block Diagram ROM / RAM interaction with 1K RAM
1KBytes internal RAM R14 R13 R12 0FDFE R11 R10 R15 R9 R8 RH0 RH1 RH2 RH3 RH4 RH5 RH6 RH7 RL0 RL1 RL2 RL3 RL4 RL5 RL6 RL7 R7 R6 R5 R4 R0 Context pointer R3 R2 0FC00 STKUV R1 R0 Stackpointer Underflow Stackpointer Stackpointer Overflow STKUV STKOV 0FA00 STKOV CPU 4

Block Diagram ROM / RAM interaction with 2K RAM
2KBytes internal RAM R14 R13 R12 0FDFE R11 R10 R15 R9 R8 RH0 RH1 RH2 RH3 RH4 RH5 RH6 RH7 RL0 RL1 RL2 RL3 RL4 RL5 RL6 RL7 R7 R6 R5 R0 Context pointer R4 R3 R2 0FC00 STKUV R1 R0 Stackpointer Underflow Stackpointer Stackpointer Overflow STKUV STKOV 0F600 STKOV CPU 4

Four Stage Instruction Pipeline at 16 MHz
Effective execution time of most instruction in 125 ns Three word prefetch queue (buscontroller) to support pipeline Optimized branch processing For branch instruction (Jump, Cond. Jump, Call, Return,...) only one additional machine cycle is normally required to fetch target instruction Jump Cache For loop processing no additional machine cycle is required CPU 4

Processing of each instruction is partitioned in 4 stages Fetch 1. Instr. 2. Instr. 3. Instr. 4. Instr. Decode Execute Write Back Time 1 Machine Cycle = 125 ns at 16 MHz CPU clock CPU 4

Processing of each instruction is partitioned in 4 stages Fetch Decode Execute Write Back 1. Instr. 2. Instr. 3. Instr. 4. Instr. Time 1 Machine Cycle = 100 ns at 20 MHz CPU clock CPU 4

Processing of each instruction is partitioned in 4 stages Fetch Decode Execute Write Back 1. Instr. 2. Instr. 3. Instr. 4. Instr. Time 1 Machine Cycle = 80 ns at 25 MHz CPU clock CPU 4

Instruction Set at 16 MHz CPU Data manipulation
Arithmetic and boolean instruction incl. fast multiply/divide in 0.6/1.2µs Multiple (up to 15) bit shift and rotate in 125 ns Bit to bit manipulation in internal RAM and SFR’s Data movement MOV instructions with all important addressing modes Byte to word conversion System stack (PUSH, POP) with over- and underflow control User stack (MOV with auto increment and decrement) ... CPU 4

...Instruction Set at 16 MHz CPU Program manipulation
Jumps and calls / conditional jumps under 16 different conditions Software- and hardware-Traps Fast context switching in 125 ns Special instructions for Power consumption reduction and system Control Non-interruptable instruction sequences Extended addressing access CPU 4

Arithmetic and boolean instruction incl. fast multiply/divide in 0.5/1.0us Multiple (up to 15) bit shift and rotate in 100 ns Bit to bit manipulation in internal RAM and SFR’s Data movement MOV instructions with all important addressing modes Byte to word conversion System stack (PUSH, POP) with over- and underflow control User stack (MOV with auto increment and decrement) ... CPU 4

...Instruction Set at 20 MHz on the 8xC166
Program manipulation Jumps and calls / conditional jumps under 16 different conditions Software- and hardware-Traps Fast context switching in 100 ns Special instructions for Power consumption reduction and system Control CPU 4

Arithmetic and boolean instruction incl. fast multiply/divide in 0.4/0.80µs Multiple (up to 15) bit shift and rotate in 80 ns Bit to bit manipulation in internal RAM and SFR’s Data movement MOV instructions with all important addressing modes Byte to word conversion System stack (PUSH, POP) with over- and underflow control User stack (MOV with auto increment and decrement) ... CPU 4

Address Space... Memory Complete address space
“von Neumann” architecture with multiple internal bus structure to avoid bus bottlenecks up to 8 MBytes address space segmented address space: 64KB code segments and 16K data pages Internal address space no ROM 1 KByte SFR's C161V C161K C161O C161RI RAM 1 KByte 1 KByte 2 KByte 3 KByte Memory 5

...Address Space Flexible ext. bus configurations to simplify system integration up to 22-bit Address / 8-bit Data MUX up to 22-bit Address / 16-bit Data MUX Five completely independent configuration registers 0-5 programmable chip selects and programmable bus control signal to save external glue-logic Memory 5

“von Neumann” architecture with multiple internal bus structure to avoid bus bottlenecks up to 16 MBytes address space segmented address space: 64KB code segments and 16K data pages Internal address space up to 128 KBytes ROM / Flash-EPROM 1 KByte SFR's Memory 5

C164RI Address Space... Memory Complete address space
“von Neumann” architecture with multiple internal bus structure to avoid bus bottlenecks up to 16 MBytes address space segmented address space: 64KB code segments and 16K data pages Internal address space 1 KByte SFR's 2 KByte RAM 64 KByte of OTP ROM Memory 5

C164RI ...Address Space Memory
Flexible ext. bus configurations to simplify system integration up to 22-bit Address / 8-bit Data (MUX) up to 22-bit Address / 16-bit Data (MUX) Five completely independent configuration registers Programmable bus control signal to save external glue-logic Memory 5

“von Neumann” architecture with multiple internal bus structure to avoid bus bottlenecks up to 16 MBytes address space segmented address space: 64KB code segments and 16K data pages Internal address space no ROM 1 KByte SFR's 2 KByte RAM Memory 5

“von Neumann” architecture with multiple internal bus structure to avoid bus bottlenecks 64KByte non-segmented address space up to 16 MBytes segmented address space: 64KB code segments and 16K data pages Internal address space up to 32 KBytes ROM / Flash-EPROM 1 KByte SFR's 83 C166 88 C166 RAM 1 KByte 1 KByte ROM 32 KByte 32 KByte Flash Memory 5

...Address Space Flexible ext. bus configurations to simplify system integration up to 18-bit Address / 8-bit Data (MUX and NMUX) up to 18-bit Address / 16-bit Data (MUX and NMUX) Two on 80C166 completely independent configuration registers Programmable HOLD/HOLDA/BREQ bus arbitration function for multi-master operations Memory 5

“von Neumann” architecture with multiple internal bus structure to avoid bus bottlenecks 64KByte non-segmented address space up to 16 MBytes segmented address space: 64KB code segments and 16K data pages Internal address space up to 128 KBytes ROM / Flash-EPROM max 4 KByte SFR's C167 C167CR RAM 4 KByte 4 KByte ROM 128 KByte Flash 128 KByte Flash Memory 5

...Address Space Flexible ext. bus configurations to simplify system integration up to 24-bit Address / 8-bit Data (MUX and NMUX) up to 24-bit Address / 16-bit Data (MUX and NMUX) Five completely independent configuration registers Five programmable chip selects and programmable bus control signal to save external glue-logic Programmable HOLD/HOLDA/BREQ bus arbitration function for multi-master operations Memory 5

Internal and external Memory Map
Segment 0 includes Internal Memory 4 M Bytes external 16 MByte internal 7 10000 512 Bytes SFR’s 0.5K Code Segments Data Pages 3FFFF 15 0FE00 C161V, C161K, C161O, C161RI: 14 Internal RAM 1K 3 0FA00 13 C161O: Internal RAM 1K 30000 12 0F600 11 Reserved 0F200 10 2 0.5K 512 Bytes Ext. SFR’s 9 0F000 20000 8 C161RI: I²C 7 Reserved 6 1 0E800 5 2K C161RI: On-Chip XRAM 4 0E000 10000 3 External Memory 2 1 Bit Addressable Space X-Bus Peripheral 00000 Memory 5

Segment 0 includes Internal Memory 7 10000 up to 16 M Bytes 512 Bytes SFR’s 0.5K Code Segments Data Pages 0FE00 3FFFF 15 Internal RAM 1K 14 3 0FA00 13 30000 12 Reserved 11 0F200 0F200 10 2 512 Bytes Ext. SFR’s 0.5K 9 0F000 0F000 20000 8 SSP Module 7 Reserved 0E800 Internal ROM/ FLASH 6 1 5 External Memory 10000 4 3 08000 Internal ROM / Flash E²PROM (mappable to Seg. 1) 2 128K Bit Addressable Space 1 X-Bus Peripheral 00000 Memory 5

Segment 0 includes Internal Memory 7 10000 up to 4 M Bytes 512 Bytes SFR’s 0.5K Code Segments Data Pages 0FE00 3FFFF 15 Internal RAM 1K 14 3 0FA00 13 Internal RAM 1K 30000 12 0F600 11 Reserved 0F200 10 2 512 Bytes Ext. SFR’s 0.5K 9 0F000 20000 8 Full -CAN 7 Reserved 0E800 Internal ROM/ FLASH 6 1 5 External Memory 10000 4 3 08000 Internal ROM / Flash E²PROM (mappable to Seg. 1) 2 64K Bit Addressable Space 1 X-Bus Peripheral 00000 Memory 5

Segment 0 includes Internal Memory 7 10000 up to 16 M Bytes 512 Bytes SFR’s 0.5K Code Segments Data Pages 0FE00 3FFFF 15 Internal RAM 1K 14 3 0FA00 13 Internal RAM 1K 30000 12 0F600 11 Reserved 0F200 10 2 512 Bytes Ext. SFR’s 0.5K 9 0F000 20000 8 7 6 1 5 External Memory 10000 4 3 2 Bit Addressable Space 1 00000 Memory 5

Segment 0 includes Internal Memory 7 10000 256 KBytes 512 Bytes SFR’s 0.5K Code Segments Data Pages 0FE00 3FFFF 15 Internal RAM 1K 14 3 0FA00 13 30000 12 11 10 2 9 External Memory 20000 8 7 Internal ROM/ FLASH 6 1 5 10000 4 3 08000 Internal ROM / Flash E²PROM (mappable to Seg. 1) 2 32K Bit Addressable Space 1 00000 Memory 5

Internal and external Memory Map - C167CR
Segment 0 includes Internal Memory 7 10000 up to 16 M Bytes 512 Bytes SFR’s 0.5K Code Segments Data Pages 0FE00 3FFFF 15 Internal RAM 1K 14 3 0FA00 13 Internal RAM 1K 30000 12 0F600 11 Reserved 0F200 10 2 9 512 Bytes Ext. SFR’s 0.5K 0F000 20000 8 Full - CAN 7 Reserved Internal ROM/ FLASH 0E800 6 1 5 External Memory 10000 4 3 08000 2 Bit Addressable Space Internal ROM / Flash E²PROM (mappable to Seg. 1) 128K 1 X-Bus Peripheral 00000 Memory 5

Code and Data Addressing via Segmentation and Paging on 8 Mbyte address range
Data addressing with Data Page Pointer (DPP) Code addressing with Code Segment Pointer 15 14 13 15 5 16-bit Adress 15 Code Seg. Pointer 16-bit Instr. Pointer Selection of one Data Page Pointer 6-bit Segment Number DPP3 16-bit DPP2 14-bit DPP1 DPP0 Page Number 8-bit Physical 22-bit Code address Physical 22-bit Data address Memory 5

Code and Data Addressing via Segmentation and Paging on 16 Mbyte address range
Data addressing with Data Page Pointer (DPP) Code addressing with Code Segment Pointer 15 14 13 15 7 16-bit Adress 15 Code Seg. Pointer 16-bit Instr. Pointer Selection of one Data Page Pointer 8-bit Segment Number DPP3 16-bit DPP2 14-bit DPP1 DPP0 Page Number 10-bit Physical 24-bit Code address Physical 24-bit Data address Memory 5

Code and Data Addressing via Segmentation and Paging on 256 KByte address range
Data addressing with Data Page Pointer (DPP) Code addressing with Code Segment Pointer 15 14 13 1 16-bit Adress 15 15 Code Seg. Pointer 16-bit Instr. Pointer Selection of one Data Page Pointer 2-bit Segment Number DPP3 16-bit DPP2 14-bit DPP1 DPP0 Page Number 4-bit Physical 18-bit Code address Physical 18-bit Data address Memory 5

Data Addressing via Data Page Pointer (DPPx)
Memory 5

Data Addressing via Extended Mode
Overrides standard DPP addressing scheme to ease large (up to 32-bit) address calculation Segment or Page override by an immediate value Segment and Page override by a Register contents Examples: Override Segment Number Override Page Number EXTS RN,#data2 ;data2:No. of instructions MOV [RM],Ri ;to be used for Ext.Addr.Mode EXTP RN, #data2 MOV [RM], Ri 15 15 15 15 RN RM RN RM 7 15 9 13 A23 A16 A15 A0 A23 A14 A13 A0 Physical address, where the contents of Ri is moved to Physical address, where the contents of Ri is moved to Memory 5

Comparison of Bus Speed at Different Bus Configurations at 16 MHz CPU Clock
single Chip 16 Bit Data 16 Bit Data 8 Bit Data 8 Bit Data 16/24 bit Address 16/24 bit Address 16/24 bit Address 16/24 bit Address Mode NON MUX MUX NON MUX MUX used Ports none Port 0, 1, 4 Port 1, 4 Port 0, 1, 4 Port 1, 4 Address Latch none none 16 Bit none 8 Bit Bus Cycle Time 125ns /../.. 125/188/250 ns 188/250/313 ns 125/188/250 ns 188/250/313 ns 0 / 1 / 2 Wait States Instr. Fetch Time 125ns /../.. 125/188/250 ns 188/250/313 ns 250/375/500 ns 375/500/625 ns 1 Word Instr. Fetch Time 2 Word 125ns /../.. 250/375/500 ns 375/500/625 ns 500/750ns/1µs 750/1µs/1.25µ EPROM Access Time t17 n.a. 88/150/213 ns 88/150/213 ns 88/150/213 ns 88/150/213 ns rel. speed for typ. code 1 1.5 2.5 3.0 4.5 (50% 2 word instructions) External bus speed optimization by prefetching into the instruction queue ! Memory 5

single Chip 16 Bit Data 16 Bit Data 8 Bit Data 8 Bit Data 16/24 bit Address 16/24 bit Address 16/24 bit Address 16/24 bit Address Mode NON MUX MUX NON MUX MUX used Ports none Port 0, 1, 4 Port 1, 4 Port 0, 1, 4 Port 1, 4 Address Latch none none 16 Bit none 8 Bit Bus Cycle Time 100ns /../.. 100/150/200 ns 150/200/250 ns 100/150/200 ns 150/200/250 ns 0 / 1 / 2 Wait States Instr. Fetch Time 100ns /../.. 100/50/200 ns 150/200/250 ns 200/300/400 ns 300/400/500 ns 1 Word Instr. Fetch Time 2 Word 100ns /../.. 200/300/400 ns 300/400/500 ns 400/600/800 ns 600/800ns/1µs EPROM Access Time t17 n.a. 70/120/170 ns 70/120/170 ns 70/120/170 ns 70/120/170 ns rel. speed for typ. code 1 1.5 2.5 3.0 4.5 (50% 2 word instructions) External bus speed optimization by prefetching into the instruction queue ! Memory 5

single Chip 16 Bit Data 16 Bit Data 8 Bit Data 8 Bit Data 16/24 bit Address 16/24 bit Address 16/24 bit Address 16/24 bit Address Mode NON MUX MUX NON MUX MUX used Ports none Port 0, 1, 4 Port 1, 4 Port 0, 1, 4 Port 1, 4 Address Latch none none 16 Bit none 8 Bit Bus Cycle Time 80ns /../.. 80/120/160 ns 120/160/200 ns 80/120/160 ns 120/160/200 ns 0 / 1 / 2 Wait States Instr. Fetch Time 80ns /../.. 80/120/160 ns 120/160/200 ns 160/240/320 ns 240/320/400 ns 1 Word Instr. Fetch Time 80ns /../.. 2 Word 160/240/320 ns 240/320/400 ns 320/480/640 ns 480/640/800ns EPROM Access Time t17 n.a. 55/105/155 ns 55/105/155 ns 55/105/155 ns 55/105/155 ns rel. speed for typ. code 1 1.5 2.5 3.0 4.5 (50% 2 word instructions) External bus speed optimization by prefetching into the instruction queue ! Memory 5

Relative Performance vs. CPU Frequency
0/1/2 Waitstates based on 0% mix of 1-word and 2-word Fetches with Data in the internal DP-RAM graph by Patrick Pettibon Memory 5

Flash technology from Siemens!
SAB C163-16F25F 128KByte FLASH CPU 1k RAM C163 Flash Module! 6

C163 Flash Comparsion with C167CR Flash
C163 Flash Module New Technology C167 Flash Module 128 KByte capacity Any use for instruction code or data Programming and erase + Progr. voltage 5V on standard VCC pins + Integrated state machine + Directly controlled by commands Programming control + Fast: 125 msec per 8 KB block Erase control + Simple erase command per sector + Fast: 10 msec per sector 128 KByte capacity Any use for instruction code or data Programming and erase - 12 V on separate VPP pin - SW controlled - Complex SW to avoid over/under- programming or erase Programming control + Fast: 200 msec per 8 KB block Erase control - Preprogramming (all zeros) necessary - Slow: 1 sec per sector C163 Flash Module 6

Embedded Flash Module Basic Overview
C163 Flash CPU Bus External Host Bus 128 KByte Flash Module C163 Core 2 Interfaces for Flash Programming C163 Flash Module 6

Basic Structure Programming Interface
External Host Interface Voltage Pumps Command & Array State Machine External Host 32K Sector 64 x 8 Assembly Buffer Programming Interfaces CPU Interface C163 Core 32 Bit Data Bus 16 Bit Address Bus C163 Flash Module 6

Programming and Erase Control on CPU Interface...
Commands for Flash Control written to Flash by CPU: Reset to Read Resets the internal state machine; returns to read mode Enter Burst Mode Enter programming mode and write first word of burst into assembly burst register Load Burst Data Write subsequent word into assembly burst register Store Burst Write last word into burst register and store whole burst into Flash array Erase Sector Erase addressed 32KByte sector Read Flash Status Read status register Clear Status Clear error flags in status register ... C163 Flash Module 6

...Programming and Erase Control on CPU Interface
Commands are transferred to Flash with command sequences for protection Cycles of command sequences are based on JEDEC standard (USA) Command sequences can only be written by instructions not fetched from Flash itself C163 Flash Module 6

Operation Control by Command Sequences
Flash Command Sequences Command Sequence of bus cycles to Flash 1. Cycle Cycle Cycle Cycle Cycle Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset to Read AAAA xxF0 RA RD Enter Burst Load AAAA xx50 WA 1.WD Load Burst Data A0F2 WD Store Burst AAAA xxAA xx55 AAAA xxA0 WA 32WD Erase Sector AAAA xxAA xx55 AAAA xx80 xxAA AAAA xx55 SA xx30 Read Status AAAA xxFA SA, R status Clear Status AAAA xxF5 R = Register Address RA = Read Data Address RD = Read Data WA = Write Address WD = Write Data SA = Sector Address (hex) All commands cycles are write cycles (exception status read cycle) ! C163 Flash Module 6

Programming a Burst of 32 Words
Programming is performed by a load / store procedure with the assembly buffer: Programming Commands Assembly Buffer Flash Array - Enter Burst Load / Load 1. Word 1. Word - Load 2. Word Flash Memory - Load 3. Word and so on 64 Byte Block - Load 31. Word Store Burst into Flash Last Word - Load 32. Word and Store Burst C163 Flash Module 6

Erasing a Sector of Flash Memory
Erasing a sector is performed in a single step: Programming Command Flash Array Only one command (sequence): Erase Sector Flash Memory Sector addressing: Sector Number Sector Size Sector Address A16 A A14...A01 32 KByte Sector SA KB SA KB SA KB SA KB Sector addresses are physical addresses ! C163 Flash Module 6

Flash Status Information
The Flash Status Register FSR provides information of the actual operating state and of error conditions to the user. Status bits in FSR: BUSY Flash Busy Busy with programming or erase; not in read mode PROG Programming State Flash busy with store burst ERASE Erase State Flash busy with erase state SE Sector Erased Addressed sector correctly erased BRST Burst Mode Assembly buffer being filled Error bits in FSR: OPER Operation Error Error during programming or erase operation VPER Voltage Error Voltage problem during Flash operation SQER Sequence Error Improper command or address in command sequence BUER Burst Error Overflow or underload condition in burst mode C163 Flash Module 6

SW control of a flash operation
A Flash operation shall be controlled by following SW procedure: 1 Write command sequence to Flash 2 Check SQER error bit for fault condition in command sequence 3 Check BUSY status bit if command is (still) in operation 4 When finished: check OPER and VPER error bits; in case of a store burst operation also the BUER error bit 5 In case of fault condition: clear error flag with a clear status command; start corrective action All addresses to Flash have to be mapped to Flash space Command, sector and data addresseshave to be located within active Flash memory space The active Flash space is that address range which is covered by the Flash C163 Flash Module 6

Features Programming Modes
64 K byte embedded OTP memory Two different programming possibilities Parallel programming mode Controlled by external standard programming system Serial programming mode Controlled by int. CPU with boot routine out of boot ROM Using e.g. a laptop as programming device External 11,5 V programming voltage Fast programming cycles: 1 word (16 bit) in 100 µs Optional read protection Interface optimized for CPU performance with 32-bit instruction fetch in one cycle Any use for instruction code or constant data OTP module 7

Comparsion of Programming Modes
Serial Programming CPU Host Mode Parallel Programming External Host Mode Host programming device Internal CPU Programming Interface Standard serial interface (USART) Automatical adjustment on baud rate Optimized for com-link of PC or laptop Programming control User SW fetched by boot ROM routine VPP control By SW: control signal on port pin Host programming device External programmer or tester Programming Interface External 16-bit system bus (XBUS) Fully asynchron OTP is slave; CPU disabled Programming control External control with bus cycles VPP control Controlled by programming device OTP 7

Basic Structure Programming Interface
Control External Host or CPU Host 32 Bit Data Bus 16 Bit Address Bus CPU Interface Array Control 64K OTP Array C164 Core OTP module 7

Overview at 16MHz... Interrupt System Interrupt Controller
Extremely short interrupt response time of minimal 312ns typical: 500ns Interrupt execution in small time segments Ensures highest real-time performance Comprehensive prioritization scheme Easy scheduling of complex real-time systems by using up to 64 priority levels (4 groups within 16 levels) Non-maskable interrupt input (NMI) Hardware-Traps on runtime errors and Software-Traps ... Interrupt System 8

...Overview at 16MHz Interrupt System
CPU independent interrupt-service via Peripheral Events Controller (PEC) Off-loads the CPU from simple but frequent interrupt-services Interrupt-driven “DMA-like” data transfer to any location in segment 0, without task switch of the CPU Makes peripheral data transfers Independent of running CPU routine Response-time is minimal 187ns, typical 375ns with a CPU load of 125ns Interrupt System 8

...Overview at 20MHz Interrupt System

Overview at 25MHz Interrupt System

Priority System, PEC Interrupt System Level 15 Level 14 L e v e l
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 group L e v e l 64 PEC 7 group 3 PEC 6 group 2 PEC 5 group 1 PEC 4 Level 15 group 0 PEC 3 PEC 2 Level 14 group 1 group 0 group 2 group 3 PEC 1 PEC 0 Level 13 group 1 group 0 group 2 group 3 Level 1-12 group 1 group 0 group 2 group 3 group 3 group 2 group 1 Level 0 group 0 Interrupt System 8

Peripheral Interrupts
Interrupt Processing Interrupt Control Register of the appropriate peripheral INTR Service: Save PSW, CSP, IP Set new priority in PSW. Set CSP, IP according to peripheral vector or Trap no. INTR Flag is Set if higher Priority Peripheral Interrupt Priority Check Group Check Peripheral Interrupt Comparison of Interrupt Priority with CPU Runtime Priority Clear INTR Flag Peripheral Interrupt External Interrupt* Peripheral Interrupt PEC Service External Interrupt* 16 Priority Levels 4 Groups * External Interrupts are possible, e.g. instead of the Capture Input C161V C161K C161O C161RI Peripheral Interrupts 15 21 21 21 Ext. Interrupts + NMI 5 5 11 11 sampled every 63 ns 4 4 7 8 Interrupt System 8

Interrupt Processing Interrupt System 12 Peripheral Interrupts
INTR Service: Save PSW, CSP, IP Set new priority in PSW. Set CSP, IP according to peripheral vector or Trap no. Interrupt Control Register of the appropriate peripheral INTR Flag is Set if higher Priority Peripheral Interrupt Priority Check Group Check Peripheral Interrupt Comparison of Interrupt Priority with CPU Runtime Priority Clear INTR Flag Peripheral Interrupt External Interrupt* PEC Service Peripheral Interrupt External Interrupt* 16 Priority Levels 4 Groups * External Interrupts are possible, e.g. instead of the Capture Input 12 Peripheral Interrupts 12 ext. Interrupts(+ NMI) including 8 which are sampled every 40 ns Interrupt System 8

Interrupt Processing Interrupt System
INTR Service: Save PSW, CSP, IP Set new priority in PSW. Set CSP, IP according to peripheral vector or Trap no. Interrupt Control Register of the appropriate peripheral INTR Flag is Set if higher Priority Peripheral Interrupt Priority Check Group Check Peripheral Interrupt Comparison of Interrupt Priority with CPU Runtime Priority Clear INTR Flag Peripheral Interrupt External Interrupt* PEC Service Peripheral Interrupt External Interrupt* 16 Priority Levels 4 Groups * External Interrupts are possible, e.g. instead of the Capture Input 32 Peripheral Interrupts on the 80C166 19 ext. Interrupts(+ NMI) Interrupt System 8

55 Peripheral Interrupts
Interrupt Processing INTR Service: Save PSW, CSP, IP Set new priority in PSW. Set CSP, IP according to peripheral vector or Trap no. Interrupt Control Register of the appropriate peripheral INTR Flag is Set if higher Priority Peripheral Interrupt Priority Check Group Check Peripheral Interrupt Comparison of Interrupt Priority with CPU Runtime Priority Clear INTR Flag Peripheral Interrupt External Interrupt* PEC Service Peripheral Interrupt External Interrupt* 16 Priority Levels 4 Groups * External Interrupts are possible, e.g. instead of the Capture Input 55 Peripheral Interrupts 36 ext. Interrupts(+ NMI) including 8 which are sampled every 50 ns Interrupt System 8

Peripheral Event Controller (PEC)
Interrupt has passed priority and group check Interrupt priority 14 or 15 and Data Counter > 0 Interrupt priority < 14 Interrupt service PEC service Memory Segment 0 0FFFF PEC Contr. Reg. INTR Service: Save PSW, CSP, IP Set new priority in PSW. Set CSP, IP according to Peripheral vector or Trap No. 8 PEC Channel Data Counter Byte or Word Transfer SRC Pointer DEST Pointer IR request if Data Counter = 0 IR request if Data Counter = 0 priority & group check 00000 Interrupt System 8

Peripherals Set of the C161x
2 General Purpose Timer units (GPT1 & GPT2) 5 Timers (250/500ns) with multiple Input/Output, Reload and Capture functions and complex concatenation capabilities Capture/Compare unit (CAPCOM) 2 timers (500ns) each with Reload register and 16 independent 16-bit Capture/Compare channels programmable to 6 modes of operation 2 independent identical USARTs max 500KBaud asynchronous max 2.0 Mbit/sec synchronous data transfer I/O Ports 6 Ports provide 76 I/O lines (V/K/O only) Watchdog: 16-bit Reload-timer causes reset on overflow Peripherals 9

Peripherals Set of the C161RI
I/O Ports 7 Ports provide 77 I/O Lines Realtime clock Fast and accurate A/D Converter 8-bit resolution, 4 input channels, 7.5µs conversion time, continuous modes I2C Bus 7 and 10-bit addressing, 400KHz 2 channels (multiplexed) Peripherals 9

Varieties of the C161 Peripherals Feature C161V C161K C161O C161RI
1 KByte 2 KByte Internal RAM Size (IRAM) 2 4 Chip Select Signals MUX (DE)MUX Bus Modes yes Power Saving Modes General Purpose Timer 1 (GPT1) Input / Output Functionality GPT1 General Purpose Timer 2 (GPT2) with Capture Input (CAPIN) Funct. Extension RAM Size (XRAM) 7 Fast external Interrupts I²C - BUS Real Time Clock (RTC) C161RI 5 8 8-Bit ADC Peripherals 9

Peripherals Set of the C163
2 General Purpose Timer units (GPT1 & GPT2) 5 Timers 160/320ns with enhanced Input/Output, Reload and Capture functions and complex concatenation capabilities Independent USART max. 780 KBaud asynchronous and max 3.1 Mbit/sec synchronous data transfer Fast Synchronous Serial Port (SSP) max Mbit/sec to connect to slave devices like EEPROMs with sending up to 3 Bytes (24bits) I/O Ports 7 Ports provide 77 I/O Lines Watchdog: 16-Bit Reload -timer causes reset on overflow Peripherals 9

Peripherals Set of the C164...
General Purpose Timer unit (GPT1) 3 Timers (200/400ns) with enhanced Input/Output, Reload and Capture functions and complex concatenation capabilities Capture/Compare unit (CAPCOM2) 2 Timers (400ns) with Reload register and 8 independent 16-bit Capture/Compare channels programmable to 6 modes of operation Capture/Compare unit (CAPCOM6) for flexible PWM Signal Generation 2 Timers (100ns) with Period register, 1 Offset register, 3/6 16-bit Capture/Compare channels and one 10-bit compare channel Optimized for Drive Control Applications ... Peripherals 9

...Peripherals Set of the C164
Independent USART max 625 KBaud asynchronous and max 2.5 Mbit/sec synchronous data transfer Fast Serial Synchronous Communication interface (SSC) max 5 Mbit/sec full duplex transfer rate, SPI compatible Fast and accurate A/D Converter 10-Bit resolution, 8 input channels, 9.7µs conversion time, enhanced continuous and scan modes with channel-injection capability, automatic calibration. I/O Ports 6 Ports provide 59 I/O lines Watchdog: 16-Bit Reload-timer causes reset on overflow Reset Detection Peripherals 9

Peripherals Set of the C165
2 General Purpose Timer units (GPT1 & GPT2) 5 Timers (160/320)ns with enhanced Input/Output, Reload and Capture functions and complex concatenation capabilities Independent USART max. 780 KBaud asynchronous and max 3.1 Mbit/sec synchronous data transfer Fast Serial Synchronous Communication interface (SSC) max Mbit/sec full duplex transfer rate, SPI compatible I/O Ports 7 Ports provide 77 I/O Lines Watchdog: 16-Bit Reload-timer causes reset on overflow Peripherals 9

Peripherals Set of the SAB 80C166...
2 General Purpose Timer units (GPT1 & GPT2) 5 Timers (200/400ns) with multiple Input/Output, Reload and Capture functions and complex concatenation capabilities Capture/Compare unit (CAPCOM) 2 timers (400ns) each with Reload register and 16 independent 16-bit Capture/Compare channels programmable to 6 modes of operation 2 independent identical USARTs max 625KBaud asynchronous max 2.5 Mbit/sec synchronous data transfer ... Peripherals 9

...Peripherals Set of the SAB 80C166
Fast and accurate A/D Converter 10-bit resolution, 10 input channels, 9.7µs conversion time, continuous and scan modes I/O Ports 6 Ports provide 76 I/O lines Watchdog: 16-bit Reload-timer causes reset on overflow Peripherals 9

Peripherals Set of the C167...
2 General Purpose Timer units (GPT1 & GPT2) 5 Timers (200/400ns) with enhanced Input/Output, Reload and Capture functions and complex concatenation capabilities 2 Capture/Compare units (CAPCOM1 & 2) 4 Timers (400ns) with Reload register and 32 independent 16-bit Capture/Compare channels programmable to 6 modes of operation 4 high resolution PWM channels each with independent time-base of up to 50ns resolution and programmable operation modes (edge-aligned, center-aligned, burst and single-shot mode) ... Peripherals 9

...Peripherals Set of the C167
Independent USART max 625 KBaud asynchronous and max 2.5 Mbit/sec synchronous data transfer Fast Serial Synchronous Communication interface (SSC) max 5 Mbit/sec full duplex transfer rate, SPI compatible Fast and accurate A/D Converter 10-Bit resolution, 16 input channels, 9.7µs conversion time, enhanced continuous and scan modes with channel-injection capability. I/O Ports 8 Ports provide 111 I/O lines Watchdog: 16-Bit Reload-timer causes reset on overflow Peripherals 9

General Purpose Timer 1 (GPT1) at 16 MHz
Three 16-bit up/down timers: 2 auxiliary timers(T2,T4) and 1 core timer(T3) Input mode Timer mode: Internal clock input with prescaler up to MHz / 500ns; Clock can be gated with external signal Counter Mode: external clock up to 1.00 MHz Cascading of core timer and any aux. timer (33-Bit timer) Count direction (C166 T3 only) can be changed externally ... GPT 1 10

General Purpose Timer 1 at 16 MHz
Output mode Interrupt possibility and toggle function at the core timer T3 Interrupt possibility at auxiliary timers T2 and T4 Reload: Core timer can be reloaded with the contents of any aux. timer Capture: Contents of the core timer can be latched into any aux. timer GPT 1 10

GPT 1 Function Diagram at 16 MHz
33-bit cascaded path Gate Run Enable Clk max 2.0 MHz Input Mode Control Reload max. 1.0 MHz Aux Timer T2 / T4 INTR Flag up / down Outp. enables Gate Run Enable Clk max 2.0 MHz Toggle Latch Input Mode Control Core Timer T3 INTR Flag max. 1.0 MHz up / down Gate Run Enable Clk max 2.0 MHz Input Mode Control Capture max. 1.0 MHz Aux Timer T2 / T4 INTR Flag up / down GPT 1 10

General Purpose Timer 1(GPT 1) at 20 MHz
Three 16-bit up/down timers: 2 auxiliary timers(T2,T4) and 1 core timer(T3) Input mode Timer mode: Internal clock input with prescaler up to 2.5 MHz / 400 ns; Clock can be gated with external signal Counter Mode: external clock up to 1.25 MHz Cascading of core timer and any aux. timer (33-Bit timer) Count direction (only T3 ) can be changed externally Output mode Interrupt possibility and toggle function at the core timer T3 Interrupt possibility at auxiliary timers T2 and T4 Reload: Core timer can be reloaded with the contents of any aux. timer Capture: Contents of the core timer can be latched into any aux. timer GPT 1 10

33-bit cascaded path Run Enable Clk max 2.5 MHz Input Mode Control Reload Aux Timer T2 / T4 INTR Flag up / down Outp. enables Gate Run Enable Clk max 2.5 MHz Toggle Latch Input Mode Control INTR Flag max. 1.25 MHz Core Timer T3 up / down to CAPCOM2 Timer T7, T8 Run Enable Clk max 2.5 MHz Input Mode Control Capture Aux Timer T2 / T4 INTR Flag up / down GPT 1 10

General Purpose Timer 1(GPT 1) at 25 MHz
Three 16-bit up/down timers: 2 auxiliary timers(T2,T4) and 1 core timer(T3) Input mode Timer mode: Internal clock input with prescaler up to 3.1 MHz / 320 ns; Clock can be gated with external signal Counter Mode: external clock up to ~1.6 MHz Cascading of core timer and any aux. timer (33-Bit timer) Count direction can be changed externally Output mode Interrupt possibility and toggle function at the core timer T3 Interrupt possibility at auxiliary timers T2 and T4 Reload: Core timer can be reloaded with the contents of any aux. timer Capture: Contents of the core timer can be latched into any aux. timer GPT 1 10

General Purpose Timer 2 (GPT 2) at 16 MHz
Two 16-Bit up/down timers (T5, T6) Input mode Timer mode: Internal clock input with prescaler up to 4MHz (250ns) Counter mode: External clock up to 2.0 MHz T5 can also be clocked with the toggle bit of T6 Output mode Interrupt possibility and toggle function of a port line (via a toggle bit) Output of T6 can be used to clock CAPCOM timers Count direction of all timers can be dynamically changed (C167) Cascading of timer T6 with timer T5 One 16-Bit Capture(for T5) / Reload(for T6) register Reload register for T6, Capture register for T5 GPT 2 11

Run Enable Clk max 4.0 MHz Input Mode Control INTR Flag max. 2 MHz Timer T5 up / down Enable Clear Enable INTR Flag Capture / Reload Reload Enable Outp. enables Toggle Latch Run Enable Clk max 4.0 MHz Input Mode Control Aux Timer T2 / T4 INTR Flag max. 2 MHz up / down 33-bit cascaded path GPT 2 11

GPT 2 Function Diagram at 16 MHz - C161RI only
Run Enable Clk max 4.0 MHz Input Mode Control INTR Flag Timer T5 up / down Enable Clear Enable INTR Flag Capture / Reload Reload Enable Toggle Latch Run Enable Clk max 4.0 MHz Input Mode Control Aux Timer T2 / T4 INTR Flag up / down 33-bit cascaded path GPT 2 11

Two 16-Bit up/down timers (T5, T6) Input mode Timer mode: Internal clock input with prescaler up to 5MHz (200ns) Counter mode: External clock up to 2.5 MHz T5 can also be clocked with the toggle bit of T6 Output mode Interrupt possibility and toggle function of a port line (via a toggle bit) Output of T6 can be used to clock CAPCOM timers Count direction of all timers can be dynamically changed (C167) Cascading of timer T6 with timer T5 One 16-Bit Capture(for T5) / Reload(for T6) register Reload register for T6, Capture register for T5 GPT 2 11

Run Enable Clk max 5.0 MHz Input Mode Control INTR Flag Timer T5 up / down Enable Clear Enable INTR Flag Capture / Reload to CAPCOM Timer T0, T1 Reload Enable Outp. enables Toggle Latch Run Enable Clk max 5.0 MHz Input Mode Control Aux Timer T2 / T4 INTR Flag up / down 33-bit cascaded path GPT 2 11

Run Enable Clk max 5.0 MHz Input Mode Control INTR Flag max. 2.5 MHz Timer T5 up / down Enable Clear Enable INTR Flag Capture / Reload to CAPCOM Timer T0, T1 Reload Enable Outp. enables Toggle Latch Run Enable Clk max 5.0 MHz Input Mode Control Aux Timer T2 / T4 INTR Flag max. 2.5 MHz up / down 33-bit cascaded path GPT 2 11

Two 16-Bit up/down timers (T5, T6) Input mode Timer mode: Internal clock input with prescaler up to 6.25MHz (160ns) Counter mode: External clock up to 3.1 MHz T5 can also be clocked with the toggle bit of T6 Output mode Interrupt possibility and toggle function of a port line (via a toggle bit) Output of T6 can be used to clock CAPCOM timers Count direction of all timers can be dynamically changed Cascading of timer T6 with timer T5 One 16-Bit Capture(for T5) / Reload(for T6) register Reload register for T6, Capture register for T5 GPT 2 11

Run Enable Clk max 6.25 MHz Input Mode Control INTR Flag max. 3.1 MHz Timer T5 up / down Enable Clear Enable INTR Flag Capture / Reload Reload Enable Outp. enables Toggle Latch Run Enable Clk max 6.25 MHz Input Mode Control Aux Timer T2 / T4 INTR Flag max. 3.1 MHz up / down 33-bit cascaded path GPT 2 11

Capture / Compare Unit (CAPCOM)
Two 16-bit timers (T0, T1) each with 16-bit reload register Timer mode: Internal clock input with prescaler up to 2.5 MHz (400ns) Counter mode: External clock input to T0 up to 1.25 MHz, output from T6 (GPT2) can be used as clock input Two units with sixteen 16-Bit Capture/Compare registers Individually programmable for Capture or any Compare mode Individually allocatable to timer T0/T1 Various Compare modes for flex. Pulse Width Modulation(PWM) Output-Pin toggles if Compare is true 1 or 2 Compare registers can operate to one output-Pin 1 or more Compare events can be detected in one timer period Interrupt only mode PWM generation - CAPCOM 12

Capture / Compare Unit 2 (CAPCOM2)
Two 16-bit timers (T7,T8) each with 16-bit reload register Timer mode: Internal clock input with prescaler up to 2.5 MHz (400ns) Counter mode: Output from T3 can be used as clock input One unit with eight 16-Bit Capture/Compare registers Individually programmable for Capture or any Compare mode Individually allocatable to timer T7/T8 Various Compare modes for flex. Pulse Width Modulation(PWM) Output-Pin toggles if Compare is true 1 or 2 Compare registers can operate to one output-Pin 1 or more Compare events can be detected in one timer period Interrupt only mode PWM generation - CAPCOM 2 12

Capture / Compare Unit 1/2 (CAPCOM 1/2)...
Four 16-bit timers (T0/T1 & T7/T8), 16-bit reload reg. each Timer mode: Int. clock input with up to 2.5 MHz (400ns) Counter mode: External clock input to T0/T7 up to 1.25 MHz, Output from T6 can be used as clock input CAPCOM 2 can be synchronized via T0 to CAPCOM 1 Two units with sixteen 16-Bit Capture/Compare registers Individually program. for Capture or any Compare mode Individually allocatable to timer T0/T1 or T7/T8 Various Compare modes for flexible Pulse Width Modulation(PWM) Output-Pin toggles if Compare is true 1 or 2 Compare registers can operate to one Output-Pin One or more Compare events can be detected in one timer period Interrupt only mode PWM generation - CAPCOM 1/2 12

CAPCOM(1) Function Diagram
T0 Reload Clk max 2.5 MHz Run Enable Input Mode Control Timer T0 INTR Flag from T6 Mode Control INTR Flag Sixteen 16 Bit Capture/ Compare Register CC0-CC15 - Capture Mode - Compare Mode 0 - Compare Mode 1 - Compare Mode 2 - Compare Mode 3 - Double Register Compare Mode 0 Edge Select for Capture Input INTR Flag Clk max 2.5 MHz Input Mode Control Timer T1 INTR Flag from T6 Run Enable T1 Reload PWM generation - CAPCOM (1) 12

CAPCOM 2 Function Diagram
T7 Reload Clk max 2.5 MHz Run Enable Input Mode Control Timer T7 INTR Flag from T6 Mode Control INTR Flag Sixteen 16 Bit Capture/ Compare Register CC16-CC33 - Capture Mode - Compare Mode 0 - Compare Mode 1 - Compare Mode 2 - Compare Mode 3 - Double Register Compare Mode 0 Channel 24 to 27 only Capture Input possible Edge Select for Capture Input INTR Flag Clk max 2.5 MHz Input Mode Control Channel 31 is able to trigger an ADC Channel Injection Timer T8 from T6 Run Enable INTR Flag T8 Reload PWM generation - CAPCOM 2 12

CAPCOM 2 Function Diagram
T7 Reload Clk max 2.5 MHz Run Enable Input Mode Control Timer T7 INTR Flag from T6 Mode Control INTR Flag eight 16 Bit Capture/ Compare Register CC16-CC19 CC24-CC27 - Capture Mode - Compare Mode 0 - Compare Mode 1 - Compare Mode 2 - Compare Mode 3 - Double Register Compare Mode 0 Channel 24 to 27 only Capture Input possible Edge Select for Capture Input INTR Flag Clk max 2.5 MHz Input Mode Control Channel 27 is able to trigger an ADC Channel Injection Timer T8 from T6 Run Enable INTR Flag T8 Reload PWM generation - CAPCOM 2 12

CAPCOM 1/2 Compare Mode 0 and 1
Several Compare events are possible within a single Timer period FFFF Compare Value 2 Reload Value Compare Value 1 is changed to Compare Register X: Value 1 Value 2 New Reload Value Mode 0: only INTR Flag is set Mode 1: INTR Flag is set and Port Pin is toggled Compare INTR Compare INTR Timer INTR Port Level P1.x P8.x (C164) PWM generation - CAPCOM 1/2 12

CAPCOM 1/2 Compare Mode 2 and 3
Only one Compare events is possible within a single Timer period FFFF Compare Value 2 Reload Value Compare Value 1 is changed to Compare Register X: Value 1 Value 2 New Reload Value Mode 2: only INTR Flag is set Mode 3: INTR Flag is set. Port Pin is set at the first Compare Event and reset at Timer overflow Timer INTR Compare INTR Port Level P1.x P8.x (C164) PWM generation - CAPCOM 1/2 12

CAPCOM 1/2 Double Register Compare Mode
Two Compare Register work together to control one Port Pin This mode is selected by a special combination of the mode 0 and 1 FFFF Compare Value 2 Reload Value Compare Value 1 Compare INTR Reg. Y Bank1 Compare Register X: (programmed to mode 1) the associated Bank2 Compare Register Y: (programmed to mode 0) Value X New Reload Value Compare INTR Reg. X Value Y Timer INTR Port Level P1.x P8.x (C164) PWM generation - CAPCOM 1/2 12

Pulse Width Modulation Unit (PWM)
4 completely indep. PWM channels each with its own time-base 50ns or 12.8µs timer-resolution provides a very wide frequency range to generate PWM signals Programmable output polarity Up to 78 KHz at 8-bit PWM resolution Four operation modes Standard, edge-aligned PWM Symmetrical, center-aligned PWM for asynchronous motor control Burst-mode for modulated PWM signals Single-shot mode 1 FPWM = =78 KHz 8-bit x 50ms PWM generation - PWM unit 12

PWM unit Frequencies and Resolution
PMW Unit Frequencies and Resolution in Mode 0 Operation (EDGE-ALIGNED) Resolution 8 Bit 10 Bit 12 Bit 14 Bit 16 Bit Input Clock 20 MHz) CPU Clock (50ns Resolution) 78.1 KHz 19.5 KHz 4.88 KHz 1.22 KHz 305 Hz CPU Clock / 64 (3.2µs Res.) 1.22 KHz 305 Hz 76.3 Hz 13.1 Hz 4.77 Hz PMW Unit Frequencies and Resolution in Mode 1 Operation (SYMMETRICAL) Resolution 8 Bit 10 Bit 12 Bit 14 Bit 16 Bit Input Clock 20 MHz) CPU Clock (50ns Resolution) 39.1 KHz 9.77 KHz 2.44 KHz 610 Hz 152.6 Hz CPU Clock / 64 (3.2µs Res.) 610 Hz 152.6 Hz 38.15 Hz 9.54 Hz 2.4 Hz PWM generation - PWM unit 12

PWM unit Function Diagramm
Period Register PP0-PP3 INTR Flag Shadow Register Comparator Run Enable 20 MHz Input Mode Control up/down,clear Timer PT0-PT3 78 KHz PWM Outputs Output Polarity Enable at 20 MHz CPU Clock Comparator Shadow Register Pulse Width Reg. PW0-PW3 4 identical PWM Channels with common Interrupt Control Register PWM generation - PWM unit 12

Contents of the Period Register (PPx)
PWM unit Mode 0 and 1... PWM Mode 0: Standard PWM’s or Edge-Aligned PWM’s PWM Mode 1: Symmetrical or Center-Aligned PWM’s Contents of the Period Register (PPx) Timer Period Timer Period Timer Period Contents of the PWx Register Contents of the PWx Register Interrupt Request and Latch of the Shadow Register IR and Latch of the Shadow Register PWM Signal PWM Signal If all channels are programmed to mode 0, edge-aligned PWM signals will be generated. A duty cycle from 0 to 100% is programmable If all channels are programmed to mode 1, center-aligned PWM signals will be generated. A duty cycle from 0 to 100% is programmable Possible PWM Signals from other channels programmed to the same mode: PWMx PWMy PWM generation - PWM unit 12

... PWM unit Modes PWM generation - PWM unit Burst Mode :
Burst Sequence by combining PWM channel 0 and 1 Single Shot : Only one PWM Pulse is generated Mode available for channel 2 and 3 Period Value Period Value Timer Period PT0 Timer Period Pulse width Value Period Value Timer is automatically stopped Timer is released by Software again Internal Signal of Channel 0 Output Signal Period of Timer PT1 The Timer can be dynamically changed to lengthen (retrigger) or shorten the output pulse Int. Signal of Channel 1 Output Result: Channel 1 is modulated by Channel 0 PWM generation - PWM unit 12

Capture / Compare Unit 6 (CAPCOM 6)
Capture Compare Unit for flexible PWM Signal Generation Optimized for Drive Control Applications C164CI suitable for All kinds of inverters Frequency converters Motor applications with current control (abc-frame, block commutation) Motor applications with speed control. Same functionality as CCU of C504 PWM generation - CAPCOM 6 12

M CAPCOM 6 - Block Diagram PWM generation - CAPCOM 6 Compare Timer T13
Period Reg. T12P Mode CTRAP Offset Reg. T12OF CC Channel 0 CC60 CC Channel 1 CC61 CC Channel 2 CC62 CC60 COUT60 Port Control Logic CC61 Compare Timer T12 COUT61 Input Control FCPU CC62 COUT62 deadtime Control Burst Mode Compare Timer T13 10 bit Input Control FCPU Comp Reg. CMP13 COUT63 CC6POS0 M Block Commutation Control Period Reg. T13P CC6POS1 CC6POS2 PWM generation - CAPCOM 6 12

CAPCOM 6 Features... PWM generation - CAPCOM 6
3-channel 16-bit capture/compare unit (CAPCOM) CAPCOM6 I/O lines : 2 outputs / channel in compare mode input in capture mode Channels independently programmable for capture or compare Compare timer T12 input clock : fCPU up to fCPU/128 Two operating modes of compare timer T12 Mode 0 : up-count and reset Mode 1 : up-count and down-count Programmable initial logic output level in compare mode 1 compare channel can generate 2 inverted signals Interrupt generation at compare timer reset / count direction change compare match / capture event PWM generation - CAPCOM 6 12

...CAPCOM 6 Features PWM generation - CAPCOM 6 External trap input
putting selectively compare outputs to low or high level Offset register for automatic constant dead-time generation 1-channel 10-bit compare unit for PWM signal generation Compare timer T13 input clock : fCPU up to fCPU/128 Edge aligned PWM (compare timer operating mode 0) PWM output at COUT3 enable/disable and output level control Combination with CAPCOM unit Burst mode Multi-channel PWM modes PWM generation - CAPCOM 6 12

CAPCOM 6 Compare Timer T12 Operation
Two count modes Operating mode 0 : 0000H up to period register value and reset Operating mode 1 : up- and down-counting between H and period register value Compare operation - match event CCx outputs toggle state when compare timer matches with compare register content COUTx outputs toggle state when compare timer matches with compare register content plus the value in the T12OF offset register ---> constant dead time generation Capture operation Storing the compare timer T12 value in the capture/compare register at a signal transition (rising/falling edge) at the CCx pin PWM generation - CAPCOM 6 12

CAPCOM 6 Compare Timer Operating Mode 0
a) Standard PWM (Edge Aligned) b) Standard PWM (Single Edge Aligned) with constant Single Edge Delay Period Value Period Value Compare Value Compare Value Offset 0000H tOff CCX CCX COUTX COUTX Both compare timers can use this operating mode PWM generation - CAPCOM 6 12

c) Symetrical PWM (Center Aligned) d) Symetrical PWM (Center Aligned) with constant Edge Delay Period Value Period Value Compare Value Compare Value Offset 0000H tOff tOff CCX CCX COUTX COUTX Only compare timer T12 can operate is this mode PWM generation - CAPCOM 6 12

Count Value T12 + T12OF 9 8 8 CCP=7 Period Reg. 1 2 3 4 5 6 7 7 7 7 6 6 6 5 5 5 T12 4 4 4 3 3 3 T12OF=2 Offset Reg. 2 2 Time Start of T12 tOff tOff Duty Cycles: CCx (CC=5) COINI Bit=0 29% COUTx (CC=5) COINI Bit=0 57% COUTx (CC=5) COINI Bit=0 57% PWM generation - CAPCOM 6 12

CAPCOM 6 Multi-Channel PWM Modes...
Special operating mode of the CAPCOM6, in which CAPCOM and COMP unit are providing versatile PWM compare output waveforms Four operating modes : Block commutation mode (e.g.for decoding of hall sensor signals) 4-pole multi-channel PWM 5-pole multi-channel PWM 6-pole multi-channel PWM ... PWM generation - CAPCOM 6 12

CAPCOM 6 ...Multi-Channel PWM Modes
Block commutation mode : Position input (CC6POS0# - CC6POS2#) controlled PWM timing generation Implementation of a specific control table for hall sensor input signals at the interrupt inputs Multi-pole multi-channel PWM modes : Compare timer T12 controlled, fixed basic PWM compare output timing pattern of active and inactive phase at 4, 5, or 6 CCx/COUTx outputs Special control register PWM generation - CAPCOM 6 12

CAPCOM 6 Block Commutation Mode...
CC6POS0# 1 1 1 Input Signals CC6POS1# 1 1 1 CC6POS2# 1 1 1 CC0 CC1 CC2 Output Signals COUT0 COUT1 COUT2 PWM generation - CAPCOM 6 12

CAPCOM 6 Block Commutation Mode
Controlled by a fixed pattern table for interrupt input signals Specific motor control mode Control table covers rotate-left/-right/idle/slow-down case for motor hall sensor input signals CCx unmodulated / COUTx modulated with compare timer T13 output PWM generation - CAPCOM 6 12

CAPCOM 6 5-Pole Multi-Channel PWM Mode...
Start Compare Timer T12 CC0 COUT1 CC2 COUT0 COUT2 or active phase Active phase modulated by Compare Timer T12 Active phase modulated by Compare Timer T13 PWM generation - CAPCOM 6 12

CAPCOM 6 ...5-Pole Multi-Channel PWM Mode
Active phase can be modulated by Compare timer T12 : modulation for two compare timer T12 periods Compare timer T13 : compare timer T13 output signal is switched to CCx or COUTx during active phase Programmable polarity of active/inactive phase PWM generation - CAPCOM 6 12

CAPCOM 6 ...Block Commutation Mode
5-Pole Multi-Channel PWM Mode: Rotate Left Mode (BCM1,0 =1,0) with COINI XX111111B Setting bit NMCS by software Bit NMCS 1 CC0 COUT1 CC2 COUT0 COUT2 1 2 3 4 5 1 2 3 4 5 1 active phase Static level during active phase (at CCx and COUTx outputs) Compare Timer T13 modulation during active phase PWM generation - CAPCOM 6 12

CAPCOM 6 Drive Applications Area
with C164CI AC Drives ("Drehstrommotoren") X Synchronous motors, Brushless DC motors ("Synchronmotoren") X Induction motors ("Asynchronmotoren") X Reluctance motors ("Reluktanzmotoren") X Stepper Motors ("Schrittmotoren") - Unipolar stepper motors ("Unipolare Schrittmotoren") X Bipolar stepper motors ("Bipolare Schrittmotoren") X DC Drives ("Gleichstrommotoren") X PWM generation - CAPCOM 6 12

Analog Digital Converter (ADC) - C161RI only
8-Bit ADC based on the successive approximation principle flexible conversion-time control with minimal 7.5µs conversion-time On-chip sample- & hold-circuit (1.5 µs sample-time) 4 multiplexed input channels Fixed channel single channel conversion Fixed channel single channel continuous conversion for permanent data tracking 8-bit result can be left- or right- adjusted to a 10-bit field Interrupt on Overrun error Conversion complete ADC 13

8-Bit A/D Converter Block Diagram - C161RI only
Channel and Mode Control Conversion Control Timing Control and Successive Approximation Register INTR Flag prescaler Com- parator INTR Flag Analog Inputs C-NET 4 Channel Analog MUX Switch Tree Result Register Reference Voltage ADC 13

Analog Digital Converter (ADC)
10-Bit ADC based on the successive approximation principle 9.7µs conversion-time On-chip sample- & hold-circuit (1.6 us sample-time) 10 multiplexed input channels Flexible operation mode Single-channel and single-channel-continuous for periodic data acquisition Auto-scan and auto-scan-continuous for permanent data tracking Easy error handling and channel identification 10-bit result and channel number in result register Overrun error check ADC 13

10-Bit A/D Converter Block Diagram
Channel and Mode Control Conversion Control Timing Control and Successive Approximation Register Channel Information Result Register INTR Flag Com- parator INTR Flag Analog Inputs C-NET 10 (16) Channel Analog MUX Switch Tree Reference Voltage ADC 13

10-Bit ADC based on the successive approximation principle 9.7µs conversion-time On-chip sample- & hold-circuit (1.6 us sample-time) 8 multiplexed input channels Automatic self-calibration after conversion Flexible operation mode Single-channel and single-channel-continuous for periodic data acquisition Auto-scan and auto-scan-continuous for permanent data tracking Channel-injection mode with own result-register can be used to interrupt the scan modes Easy error handling and channel identification 10-bit result and channel number in result register Overrun error check ADC 13

10-Bit ADC based on the successive approximation principle 9.7µs conversion-time On-chip sample- & hold-circuit (1.6 us sample-time) 16 Multiplexed input channels Automatic self-calibration after conversion Flexible operation mode Single-channel and single-channel-continuous for periodic data acquisition Auto-scan and auto-scan-continuous for permanent data tracking Channel-injection mode with own result-register can be used to interrupt the scan modes Easy error handling and channel identification 10-bit result and channel number in result register Overrun error check ADC 13

10-Bit A/D Converter Block Diagram
Channel and Mode Control Conversion Control Timing Control and Successive Approximation Register INTR Flag Com- parator INTR Flag Analog Inputs C-NET 8 (16) Channel Analog MUX Switch Tree Reference Voltage Channel Information Result Register Channel Selection Result Register for Channel Injection Mode ADC 13

Asynchronous / Synchronous Serial Channel (USART) at 16MHz
Synchronous / asynchronous serial channel with its own baud-rate-generator Asynchronous mode with max 500 KBaud transfer rate Full duplex (receive and transmit at the same time) programmable features: 1 or 2 stop bits, 7, 8 or 9 data bits Generation of parity- or wake-up bit at data transmission Odd or even parity Error detection (parity, overrun, framing) Wake-up check (receive int. flag is set if wake-up bit is true) Synchronous mode with max 2.0 Mbit/sec transfer range Half duplex operation (only transmit or receive possible) Easy I/O expansion with external shift register Overrun error detection USART 14

Transmit Shift Register Receive Shift Register
USART Block Diagram CPU CLK Baud Rate Generator from internal Bus Asynchronous/ Synchronous Port Pin INTR Flag Transmit Transmit Shift Register Shift CLK INTR Flag Receive Control Unit Port Pin Receive Shift Register INTR Flag ERROR Receive Buffer to internal Bus Control Reg. USART 14

Synchronous Serial Channel (SSC), SPI compatible at 16MHz
Full duplex Synchronous Serial Channel (SSC) with its own baudrate generator for high speed communication Up to 4 Mbit/sec transfer rate SPI compatible Master (clock is output) or slave mode (clock is input) Programmable features to satisfy various communication requirements MSB or LSB first Data frame from one to 16-bit Clock polarity and phase USART 14

Synchronous Serial Channel (SSC), SPI compatible at 20 MHz
Full duplex Synchronous Serial Channel (SSC) with its own baudrate generator for high speed communication Up to 5 Mbit/sec transfer rate SPI compatible Master (clock is output) or slave mode (clock is input) Programmable features to satisfy various communication requirements MSB or LSB first Data frame from one to 16-bit Clock polarity and phase USART 14

Synchronous Serial Channel (SSC), SPI compatible at 25MHz
Full duplex Synchronous Serial Channel (SSC) with its own baudrate generator for high speed communication Up to 6.25 Mbit/sec transfer rate SPI compatible Master (clock is output) or slave mode (clock is input) Programmable features to satisfy various communication requirements MSB or LSB first Data frame from one to 16-bit Clock polarity and phase USART 14

Synchronous Serial Channel - Block Diagram
CPU Clock Baud Rate Generator Master Mode SSCCLK Clock Control Slave Mode Master / Slave Selection SSCDO Shift Register programmable from bit SSCDI Control Unit with Control and Status Registers MSB- / LSB-First Selection Interrupt Request Receive Buffer Transmit Buffer Internal Bus SSP 15

Synchronous Serial Port (SSP)
Synchronous Serial Port was designed for communication with external slave devices such as EEPROMs SSP can be programmed to... send command, address or data information to a peripheral receive data from a peripheral Three-wire interface compatible to SPI-protocol Bi-directional serial data line Configurable clock control line Two dedicated configurable chip enable lines Baudrate up to 12.5 Mbit/s Heading selectable (LSB / MSB first) Busy flag (Check if SSP is busy or idle) Interrupt (XP1INT) is generated at the end of a transfer SSP 15

Synchronous Serial Port Block Diagram
SSPCE0 (P4.5) Chip Output Control Logic Enable Control SSPCE1 (P4.4) Control Baudrate Clock Output SSPCLK (P4.7) Generator Control Control SSPCON1 Shift Unit & Shift Control SSPTB0/ SSPRB0 Input / Output Control SSPDAT (P4.6) SSPTB2 SSPTB1 SSPCON0 8 bit 8 bit 8 bit Interrupt (XP1INT) In order to use the SSP, - Bit XPEREN (SYSCON.2) must be set during initialization (before EINIT instruction) - Pins P4.4 to P4.7 must not be used as segment address lines (max. 5 x 1 Mbyte external memory) XBUS-Interface SSP 15

Synchronous Serial Port Detailed Block Diagram
XBCON XADRS INTERNAL BUS X-BUS CONTROLLER 8 8 8 SSPCON0 SIN SSPTB0/ SSPRB0 SOUT SIN SOUT SIN SOUT SDATA I/O (P4.6) SSPTB1 SSPTB2 1 1 1 SSPCON1 Clock Generator SCLK (P4.7) Shift / Load 1-Byte 2-Byte CONTROLLER SSP 3-Byte SSPCE1 (P4.4) CS1 SSPCE0 (P4.5) CS0 SSP 15

Synchronous Serial Port Configurations...
Configuration of the Chip Enable lines: Chip Enable lines may be selected separately: no Chip Enable line selected Chip Enable line 0 (SSPCE0) selected Chip Enable line 1 (SSPCE1) selected Both Chip Enable lines selected (take care with READ-operations) Polarity can be selected for each Chip Enable line (active high / active low) SSP 15

...Synchronous Serial Port Configurations
Configuration of the Clock line (like SSC on C167/C165) Clock polarity can be selected: Idle Clock line high (leading clock edge is high-to- low transition) Idle Clock line low (leading clock edge is low-to-high transition) Clock edge can be selected: Shift data on leading clock edge, latch on trailing edge Latch data on leading clock edge, shift on trailing edge SSP 15

Differences between SSP and SSC
SSP (C163) SSC Synchronous Serial Port Synchronous Serial Channel Up to MHz CPU Up to 5 20 MHz CPU clock clock Only half duplex communication Full duplex communication possible; possible; one bidirectional data line two data lines (Transmit, Receive) Shift clock can only be generated Shift clock can be generated (master only) (master) or received (slave) Data width 1 byte Data width can be chosen from 2 bits to 16 bits No error detection mechanisms Error detection mechanisms Two dedicated chip enable lines No dedicated chip enable lines Connected to XBUS Connected to Internal Bus 1 interrupt source dedicated to SSP 3 interrupt sources dedicated to SSC SSP vs. SSC 16

Serial E2PROM connected to SSP
EEPROM (e.g. X25C02) P4.4 / SSPCE1 CS# (Chip Select) P4.5 / SSPCE0 SO (Serial Data Output) P4.6 / SSPDAT SI (Serial Data Input) SCK (Clock) P4.7 / SSPCLK Application for the SSP 17

Single Write Operation to EEPROM (X25C02)
SSPCLK SSPDAT Write Enable >500 ns Write Command Address (e.g. A5h) Data (e.g. 99h) SSPCE0/1 SSPTB0 = 0x06; /* Write Enable */ SSPTB2 = 0x02; /* Write Command */ SSPTB1 = 0xA5; /* Address */ SSPTB0 = 0x99; /* Data */ Note: - After the data has been written, the EEPROM needs 10 ms to store the data. - SSPCON 0 and SSPCON 1 must be configured before the operation. Application for the SSP 17

Single Read Operation to EEPROM (X25C02)
one clock-cycle needed for EEPROM to respond SSPCLK SSPDAT Read Command Address (e.g. A5h) Data (e.g. 99h) sent by EEPROM SSPCE0/1 SSPTB1 = 0x03; /* Read Command */ SSPTB0 = 0xA5; /* Address */ Note: SSPCON 0 and SSPCON 1 must be configured before the operation. Application for the SSP 17

Siemens, The CAN Reference!
CAN Bus 18

User Benefits... CAN Bus CAN is low cost
Serial bus with two wires: good price/performance ratio Low cost protocol devices available driven by high volume production in the automotive and industrial markets About CAN nodes in use so far CAN is reliable Sophisticated error detection and error handling mechanisms results in high reliability transmission Example: 500 kbit/s, 25% bus load, 2000 hours per year: One undetected error every 1000 years Erroneous messages are detected and repeated Every bus node is informed about an error High immunity to Electromagnetic Interference ... CAN Bus 18

...User Benefits... CAN Bus CAN means real-time
Short message length (0 to 8 data bytes / message) Low latency between transmission request and actual start of transmission Inherent Arbitration on Message Priority (AMP) Multi Master using CSMA/CD + AMP method CAN is flexible CAN Nodes can be easily connected / disconnected (i.e. plug & play) Number of nodes not limited by the protocol CAN is fast maximum data rate is 1 40 m bus length (still about m bus length) ... CAN Bus 18

...User Benefits CAN Bus CAN allows Multi-Master Operation
Each CAN node is able to access the bus Bus communication is not disturbed by faulty nodes Faulty nodes self swith-off from bus communication CAN means Broadcast Capability Messages can be sent to single/multiple nodes All nodes simultaneously receive common data CAN is standardized ISO-DIS (high speed applications) ISO-DIS (low speed applications) CAN Bus 18

Higher Layer Protocols...
CAN Application Layer (CAL) Layer-7-standard defined by CiA (CAN in Automation) Network management service provides initialisation, surveillance and configuration of nodes in a standardized way Takes care of all aspects for the realisation of open communication via CAN (makes sure manufacturer-specific systems work together) Available implementations of CAL make it easy for the user to define sophisticated standardized Controller Area Networks ... CAN Bus 18

...Higher Layer Protocols
CANopen (CiA DS-301) Application profile based on CAL While CAL determines the way of communicating, an Application Profile determines the meaning of specific messages for the respective application Target: device interchangeability for certain applications Further higher level protocols / standards: Automotive Sector: VOLCANO, OSEK (in development) Industrial Automation: DeviceNet (Allen Bradley), SDS (Honeywell) CAN Bus 18

Application Examples... CAN Bus
CAN in motor vehicles (cars, trucks, buses) Enables communication between ECUs like engine management system, anti-skid braking, gear control, active suspension ... (power train) Used to control units like dashboard, lighting, air conditioning, windows, central locking, airbag, seat belts etc. (body control) CAN in utility vehicles e.g. construction vehicles, forklifts, tractors etc. CAN used for power train and hydraulic control ... CAN Bus 18

...Application Examples... CAN Bus CAN in trains
High need of data exchange between the different electronic subsystem control units Mainly data about acceleration, braking, door control, error messages etc. but also for diagnosis CAN in industrial automation Excellent way of connecting all kinds of automation equipment (control units, sensors and actuators) Used for initialization, program and parameter up-/download, exchange of rated values / actual values, diagnosis etc. Machine control (printing machines, paper- and textile machines etc.): Connection of the different intelligent subsystems Transport systems ... CAN Bus 18

...Application Examples CAN Bus CAN in medical equipment
Computer tomographs, X-ray machines, dentist chairs, wheel chairs CAN in building automation Heating, air conditioning, lighting, surveillance etc. Elevator and escalator control CAN in household appliances Dishwashers, washing machines, even coffee machines... CAN in office automation photo copier, interface to document handler, paper feeding systems, sorter communicates status, allows in field connection or "hot swapping" DocuText Systems, i.e. automatic print, sort and bind on demand CAN Bus 18

Some things worth knowing about CAN...
Developed in the mid-eighties by BOSCH Asynchronous serial bus with linear bus structure and equal nodes (Multi Master bus) CAN does not address nodes (address information is inside the messages combined with message priority) Two bus states: dominant and recessive Bus logic according to "Wired-AND" mechanism: dominant bits (Zeros) override recessive bits (Ones) Bus Access via CSMA/CD with NDA (Carrier Sense Multiple Access/ Collision Detection with Non-Destructive Arbitration) CAN Bus 18

...Some things worth knowing about CAN
recessive NODE A dominant recessive NODE B dominant bus idle recessive CAN BUS dominant Node B sends out recessive but reads back dominant level Node B loses arbitration and switches to receive CAN Bus 18

Typical CAN node structure
Node A Node B e.g. ABS e.g. EMS Application e.g. 80C166 e.g. C167CR or C515C Host-Controller e.g. SAE81C90 (more nodes) CAN-Controller CAN CAN- Transceiver CAN_H CAN-Bus UDiff CAN_L CAN Bus 18

CAN Data Frames... CAN Bus There are mainly two ways of communicating:
One node is 'talking', all other nodes 'listen' Node A is asking Node B for something and gets the answer. To 'talk', CAN nodes use Data Frames. A Data Frame consists of an Identifier, the data to be transmittedand a CRC-Checksum. Identifier Data Field (0..8 Bytes) CRC-Field CAN Bus 18

...CAN Data Frames The identifier specifies the contents of the message ('engine speed', 'oil temperature', etc.) and the message priority The Data Field contains the corresponding value ('6000 rpm', '110°C', etc.) The Cyclic Redundancy Check is used to detect transmission errors. All nodes receive the Data Frame. Those who do not need the information, just don't store it. CAN Bus 18

CAN Basics... To 'ask' for information, CAN nodes use Remote Frames. A Remote Frame consists of the Identifier and the CRC-Checksum. It contains no data. The identifier contains the information that is requested ('engine speed', 'oil temperature', etc.) and the message priority. The node that is supposed to provide the requested information (e.g. the sensor for the oil temperature) does so by sending the corresponding Data Frame (same identifier, the Data Field contains the desired information). Identifier CRC-Field CAN Bus 18

...CAN Basics CAN Bus How hot is the oil ? 115 °C !
Data Frame; Identifier 'oil_tmp'; contains desired information ~~~~~ Remote Frame; Identifier 'oil_tmp' Node A Node B (oil temp.- sensor) How hot is the oil ? 115°C 115 °C ! CAN Bus 18

Standard CAN / Extended CAN...
Most CAN nodes talk in the 'language' that most other CAN nodes understand: They use Standard Data or Remote Frames. A Standard Frame contains an identifier which is 11 bits long. With this 11 bits, 211 (=2048) different messages can be addressed. CAN nodes using Standard-CAN-Frames use the CAN Specification Version 2.0A. Some CAN nodes talk with a special 'accent': They use Extended Data or Remote Frames. An Extended Frame contains an identifier which is 29 bits long. ... CAN Bus 18

...Standart CAN / Extended CAN...
Over 536 million (229) different messages can be addressed. CAN nodes using Extended-CAN-Frames use the CAN Specification Version 2.0B (active). Some Standard-CAN nodes don't understand this 'accent', but they tolerate it and just don't care. If an Extended Frame is 'on the air', these CAN nodes cannot store the data, but they as well do not produce errors. These CAN nodes use CAN Version 2.0A, but are also known as Version 2.0B passive. They can be used in a Controller Area Network where Extended Frames are used. ... CAN Bus 18

...Standart CAN / Extended CAN
Some Standard-CAN nodes don't understand and also don't tolerate this 'accent'. If an Extended Frame is 'on the air', these CAN nodes produce errors. These CAN nodes use only CAN Version 2.0A. They can not be used in a Controller Area Network where Extended Frames are used. 16 bit parts: C167CR, C164CI: V2.0B active CAN Bus 18

Basic CAN / Full CAN... CAN Bus
In some CAN controllers, only the basic CAN functions are implemented. They are called Basic-CAN controllers. Mostly there's only one transmit buffer and one or two receive buffers for transmission and reception of the Data- / Remote Frames. Each incoming message is stored. The host CPU has to decide whether the message data is needed or not. Therefore these controllers should only be used in CANs with very low baudrates and/or very few messages because of the high CPU load. Advantage: They use the least possible silicon area. ... Host CPU Messages to be sent Received Messages Receive Buffer CAN Bus low high Transmit Buffer CPU load Basic-CAN Controller CAN Bus 18

...Basic CAN / Full CAN... CAN Bus
In the other CAN controllers, also message management and acceptance filtering are implemented. They are called Full-CAN controllers. There are several Message Objects, each with its own identifier. Only if a message for one of these preprogrammed identifier is received, it is stored and the CPU is interrupted. In this way, the CPU load is low. ... Message Object 1 Message Object 2 Accep- tance Filtering Message Manage- ment CAN Bus . low high Message Object n CPU load Host CPU Full-CAN Controller CAN Bus 18

...Basic CAN / Full CAN CAN Bus
All Siemens CAN-Controllers are Full-CAN controllers. But they also provide Basic-CAN functionality one message object can be used like a Basic CAN receive register CAN Bus 18

Features of the CAN Module on C167CR / C164CI...
Functionality corresponds to AN 82527 Complies with CAN spec V2.0B active (Standard- und Extended-CAN) Maximum CAN Transfer Rate (1 MBit/s) Full CAN Device 15 Message Objects with their own identifier and their own status- and control bits Each Message Object can be defined as Transmit- or Receive Object ... CAN Module 19

...Features of the CAN Module on C167CR / C164CI
Programmable Mask Registers for Acceptance Filtering Global Mask for incoming Messages (Full-CAN-Objects) Additional Mask for Message Object 15 (Basic-CAN-Feature) Basic CAN Feature (Message Object 15) Equipped with two Receive Buffers Own Global Mask Register for Acceptance Filtering Connection to the Host CPU (C166-Core) Module access via chip-internal XBUS (16-bit demultiplexed mode) Interrupt connection to the CPU; Flexible interrupt event control To connect the application to CAN only a CAN transceiver is needed CAN Module 19

Connecting the to CAN CAN Module C167CR/C161CI CAN-Bus Transceiver
CAN_L CAN_H P4.5 Pa.b CAN_RxD Receive CAN_H Connection P4.6 to the CAN_TxD Transmit Application CAN_L Pc.d P2.0 (Standby) R(opt) Vref n.c. CAN Module 19

I2C module C161RI only µC I2C module 7 and 10-bit addressing, 400KHz
2 channels (multiplexed) master mode slave mode multimaster mode SDAx SDA0 SCL0 SCLx Output Control Generic data line clock line I²C Module µC I2C module 20

Real Time Clock (RTC) - C161RI / C164CI
Counts Time Ticks Time Ticks are defined by external crystal frequency and programmable prescaler (trim register) Cyclic time based Interrupt (see separate foil) Cycle Time can be adjusted via Reload Register (trim register) Interrupt Request on XPER3 Interrupt Node Additional Function RTC register and programmable prescaler can be concatenated to build a 48-bit timer unit Real Time Clock 21

RTC Block Diagram Real Time Clock Programmable Divider Trim Register
Interrupt 16 bit Reload Value RTC High RTC Low XTAL T 14 8 bit Prescaler RTC Clock Driver Oscillator 32-bit Timer 16-bit Timer Time between two Interrupts Oscillator Frequency Minimal Time Maximal Time Possible Time Base RTC 4 MHz 0.064 ms 4.1 s 1 s Crystal or external Oscillator 5 MHz 0.052 ms 3.35 s 1 s 8 MHz 0.032 ms 2 s 1 s 10 MHz 0.026 ms 1.6 s 1 s 12 MHz 0.022 ms 1.3 s 1 s 16 MHz 0.016 ms 1 s 1 s external Oscillator 20 MHz 0.013 ms 0.8 s 0.1 s 24 MHz 0.011 ms 0.6 s 0.1 s Real Time Clock 21

RTC Cyclic time based Interrupt
Active Mode with flexible Peripheral Management Active Mode with flexible Peripheral Management IDLE MODE 1 Cycle Combination of Active Mode and Idle Mode During Active Mode all not used peripherals are disabled (Flexible Peripheral Management) Cyclic waking up from Idle Mode to Active Mode via programmable RTC interrupt Waking up on external events via interrupt (ASC, SSC, CAN, EXIN) Real Time Clock 21

Watchdog Timer (WDT) at 16 MHz
16-Bit timer overflow results in: Software reset Pulls RSTOUT Pin low Sets identification bit and leaves WDT enabled Programmable input clock High Byte reload register Timer period from 32µs to 588ms Can be reloaded with a special instruction Watchdog 22

16-Bit timer overflow results in: Software reset Pulls RSTOUT Pin low Sets identification bit and leaves WDT enabled Programmable input clock High Byte reload register Timer period from 25.6µs to 470ms Can be reloaded with a special instruction Watchdog 22

16-Bit timer overflow results in: Software reset Pulls RSTOUT Pin low Sets identification bit and leaves WDT enabled Programmable input clock High Byte reload register Timer period from 20.5µs to 376ms Can be reloaded with a special instruction Watchdog 22

WDT Block Diagram Watchdog WDT control 8-bit reload zero service WDT
RSTOUT on overflow CPU CLK / 2 16-bit Timer Software Reset high Byte low Byte CPU CLK / 128 WDT control Watchdog 22

System Clock Features PLL
On-chip PLL circuit implemented Variety of different clock options available: System Clock can be selected to be 0.5, 1, 1.5, 2, 2.5, 3, 4 and 5 times the externally applied frequency at the XTAL-pins In case of external clock failure: PLL Unlocked Interrupt (XP3INT) is generated PLL runs on its base frequency ( MHz) C164 and C163 can perform emergency operation External clock is monitored even if clock options 'W' (direct clock drive) or '0.5' (prescaler mode) are selected PLL 23

Clock Options PLL Note fOSC : f CPU fCPU fCPU fCPU fCPU fCPU fCPU fCPU
factor Pre- scalar P0H7 P0H6 P0H5 Note fOSC : f CPU fOSC 1 1 1 4 4 OFF default fCPU fOSC 1 1 2 2 OFF fCPU fOSC 1 1 3 3 OFF fCPU fOSC 1 5 5 OFF fCPU direct clock drive fOSC 1 1 W OFF OFF fCPU prescalar mode fOSC 1 0.5 OFF ON fCPU fOSC 1 1.5 3 ON fCPU fOSC 2.5 5 ON fCPU 0 = external pull- down PLL 23

Power Management Modular Version 2.0
24

Modular Design Overview
Power Management Power Saving Modes Flexible Clock Generation Management Flexible Peripheral Management Real Time Clock Power Management 24

Power Saving Modes Power Management IDLE Mode
Disabling of CPU and internal memory modules All peripherals can be enabled Enabling of CPU via interrupt Power Down Mode Disabling of complete controller functionality Optional running of real time clock Optional disabling of port output drivers (tristate) Preservation of internal RAM content for VCC voltage higher than 2.5 V Enabling of controller functionality via reset Power Management 24

Flexible Clock Generation Management Clock Sources
Basic Clock Source Selection between different sources via port 0 configuration Direct drive (fCPU = fOSC) Prescaler (fCPU = fOSC / 2) PLL (fCPU = f OSC * PLLfactor) Selection can not be changed via software Slow Down Divider Clock Source Programmable oscillator clock divider (fCPU = fOSC / SDD factor) Dividing factor can be changed by software Optional lower frequency via second 32 kHz crystal (C161RI only) Power Management 24

Flexible Clock Generation Management Overview
32 kHz Software SYSCON2.SOSC XTAL3 fOSC2 OSC2 XTAL4 fOSC M U X SDD fCPU M U X M U X PLL Direct Drive 2:1 XTAL1 fOSC1 OSC1 Software XTAL2 Clock Detection Hardware Selection on Reset 32:1 fRTC M U X RCD Software SYSCON2.RSC C161RI only Power Management 24

Flexible Clock Generation Management Slow Down Divider (SDD) - Features
Significant reduction of power consumption Reduced CPU frequency by programmable clock divider 5-bit Reload Counter for programmable divider with factor 1-32 fCPU = fOSC / SDD factor (e.g. 16 MHz / 32 = 0.5 MHz) Notes: Output CLKOUT also shows the reduced frequency No OWD available, if PLL is stopped during Slow Down Clock Generation Power Management 24

Flexible Clock Generation Management Slow Down Divider (SDD)
CLKREL Reload fOSC fSDDOUT Reload Counter fOSC fSDDOUT CLKREL=3 CLKREL=5 CLKREL=6 CLKREL=9 Power Management 24

Flexible Clock Generation Management Optimized Oscillator
Oscillator Start-up voltage  3 V power supply Stable oscillation down to 2.7 V Minimum oscillator power consumption at 3 V power supply (oscillator only) Crystal frequency range: 3.5 MHz  fcrystal  16 MHz External oscillator input frequency range: 1 MHz  foscillator  40 MHz Power Management 24

Flexible Clock Generation Management Register Definition
SYSCON2 Flexible Clock Generation Management CLK LOCK CLKREL CLKCON SOSC RSC PDCON SYSRLS New Bit comparing to V1.1 Moved Bit comparing to V1.1 Power Management 24

Flexible Peripheral Management Features
Peripherals organized in groups with seperate clock drivers Interface Clock Driver (ICD): ASC0, SSC, WDT, Interrupt Detection Peripheral Clock Driver (PCD): all other Peripherals, Interrupt Controller, Ports RTC Clock Driver (RCD): Real Time Clock Disabling of Peripherals PCD including all connected Peripherals can be disabled Each Peripheral can be disabled individually All registers are visible for read and write access while a peripheral is disabled individually Peripheral continues operation after re-enabling Power Management 24

Flexible Peripheral Management Overview: C161RI
CLK CPU CLK EN CPU Clock Driver IDLE CLK MEM Peripherals CLK EN Peripheral Clock Driver CLK ADC EN SW SW CLK GPT1 EN fCPU SW CLK Interface Clock Driver CLK GPT2 EN SW CLK Int. Detection CLK I2C EN SW CLK ASC EN CLK Ports SW CLK SSC EN CLK Interrupt Controller New SW Modified CLK WDT Power Management 24

Flexible Peripheral Management Overview: C164CI
CLK CPU CLK EN CPU Clock Driver IDLE CLK MEM Peripherals CLK EN Peripheral Clock Driver CLK ADC EN SW SW CLK GPT1 EN fCPU SW CLK Interface Clock Driver CLK CAP COM2 EN SW CLK Int. Detection CLK CAP COM6 EN SW CLK ASC EN CLK CAN EN SW SW CLK SSC EN CLK Ports New SW Modified CLK Interrupt Controller CLK WDT Power Management 24

Flexible Peripheral Management Register Definition
SYSCON3 Flexible Peripheral Management PCD DIS CAN2 DIS CAN1 DIS SSP DIS I2C DIS PWM DIS CC6 DIS CC2 DIS CC1 DIS GPT2 DIS GPT1 DIS SSC DIS ASC0 DIS ADC DIS - - New Bit comparing to V1.1 Moved Bit comparing to V1.1 Power Management 24

Real Time Clock (RTC) Features
Counts Time Ticks Time Ticks are defined by external oscillator frequency divided by 32 fixed prescaler (8:1) programmable prescaler (trim register) Cyclic time based interrupt Cycle time can be adjusted via reload register (trim register) Interrupt request shared with PLL interrupt Additional Function RTC register and programmable prescaler are concatenated to built a 48-bit timer unit Power Management 24

Real Time Clock (RTC) Power Management Programmable Prescaler T14REL
Reload Cyclic Interrupt fRTC 8:1 T14 RTCL RTCH Optional second 32 KHz crystal Crystal or external Oscillator external Oscillator Power Management 24

Real Time Clock Interrupt Sharing
ISNC Interrupt Sub Node Control PLL IE PLL IR RTC IE RTC IR - - - - - - - - - - - - New Bit comparing to V1.1 Moved Bit comparing to V1.1 Power Management 24

Power Consumption Overview
Active Mode Flexible Peripheral Management Active or Idle Mode S L O W D N Active Mode and disabled Peripherals Existing Features Idle Mode New Features Flexible Peripheral Management Idle Mode and disabled Peripherals Power Down Mode Ports: ON RTC / OSC: ON Power Down Mode Ports: OFF RTC / OSC: ON Active or Idle Mode Power Down Mode Ports: ON RTC / OSC: OFF Power Down Mode Ports: OFF RTC / OSC: OFF Power Management 24

SYSCON2/3 Access Procedure State Machine
Note: This sequence can be executed in an ATOMIC sequence only! Power Management 24

SYSCON2/3 Access Procedure Programming Example
EXTR #1 ESFR access BFLDL SYSCON2, #0Fh, #00h set SYSRLS to 0000b EXTR #4 ESFR access BFLDL SYSCON2, #0Fh, #09h set SYSRLS to 1001b MOV SYSCON2, #0003h set SYSRLS to 0011b BSET SYSCON2.2 set SYSRLS to 0111b access to SYSCON2 / SYSCON3 enabled; e.g.: BFLDH SYSCON2, #03h, #02h set CLKCON to 10b => switch to SDD clock => disable PLL (if implemented) Power Management 24

Overview Port Structure
The Port lines provide the connection to the external world 77 Port lines on the SAB 80C166 111 Port lines on the C167 77 Port lines on the C165/C163 59 Port lines on the C164 64 Port lines on the C161V/K/O 77 Port lines on the C161RI All Port lines are individually addressable and all I/0 lines are independently programmable for input or output Each Port line is dedicated to one or more peripheral functions Each Port is protected with fast diodes Programmable open drain buffers P2, 3, 6, 7, 8 on the C167 P3, 8 on the C164 Ports 25

VCC Alternate Output Alternate Enable Direction Register Write Output Latch Port Pin Mux Buffer Read Direction Internal Bus Buffer Mux Input Latch Vss ESD structure Clock Alternate Input Ports 25

VCC Alternate Output Alternate Enable Direction Register Open Drain Control Write Output Latch Port Pin Mux Buffer Read Direction Internal Bus Buffer Mux Input Latch Vss ESD structure Clock Alternate Input Ports 25

The Summary of the C166 Family
WDT OSC. PEC CPU ROM / RAM PORTS CAPCOM ADC Bus Ext. Processor -System Interrupt-System USART GPTs Peripheral-System Flash Control X-Bus Sync Communication PWM Periphrl. Summary 26

Processor System Summary
High Computational Power: min 80ns Instruction Cycle Time Fast algorithms (short sample times for closed loop control) Fast task execution Control Oriented Instruction Set Boolean processing / bit-handling and processing Task switch / power saving General Purpose Register Oriented Architecture Managing of multiple quasi-parallel tasks Powerful Addressing Capabilities Large address range and powerful addressing modes (HLL) On-chip RAM, OTP/ROM/Flash For very fast Memory Access In-System reprogrammable Flash Memory one-time programmable ROM Summary 26

Interrupt System Summary
Extremely Short Interrupt Response Time of typically min. 320ns Interrupt execution in small time segments Ensures highest real-time performance Comprehensive Prioritization Scheme Easy scheduling of complex real-time systems by using up to 64 Priority levels (4 groups within 16 levels) CPU-Independent Interrupt Service via Peripheral Events Controller (PEC) Off-loads the CPU from simple but frequent interrupt-services Interrupt-driven “DMA-like” data transfer, without task switch of CPU Makes peripheral data transfers independent of running CPU routine Summary 26

Peripheral System Summary
Multi-functional Timer/Counter Units (up to 5 Timers / Counters) with Complex Concatenation Possible Comprehensive up tp 32 Channel Capture/Compare Unit with up to 4 Allocatable Time-Bases Capture/Compare unit (CAPCOM6) for flexible PWM Signal Generation 4 high resolution PWM channels up to 10-bit Multi-Functional A/D-Converter for Fast Data Acquisition in Control Systems Summary 26

Peripheral System Summary
Bi-directional, Protected and Individually Programmable External Port-Lines Serial Communication Interfaces Standard asynchronous communication Fast synchronous communication in master- & slave-mode (SPI) Easy Adaptation to Special Application or Customer Requirements via Internal X-BUS Architecture CAN-Bus, Profibus, SSP, etc. flexible Power Management Summary 26

2-chip Emulation Technology
One Bondout chip supports emulation of all related derivatives, new or existing (i.e. C167, C165, C163, C161) New X-Peripherals (XPERs) are emulated using the standard chip In emulation mode the standard IC is sleeping and only the XPER is active. The Bondout chip has full access to the XPER over a particular port No need for Bondout redesign User has full emulation control over the XPER without any intrusion of real-time Full access to target system is maintained Supported by all major tool manufacturers Development Tools 27

2-chip Emulation Technology
Development Tools 27

Development Tools are a constant factor of success for Siemens Microcontrollers...
Directory ...just as Siemens Microcontrollers are a constant factor of success for the products they are designed into! Development Tools 27

pls Major Tool Partners hitex KEIL TASKING i+ME INFORM Tektronix dli
Emulators hitex LAUTERBACH YOKOGAWA KONTRON ELEKTRONIK KEIL Software Compilers, Assemblers HIGHTEC TASKING CAN/FUZZY i+ME INFORM stzp MicroFuzzy Tektronix dli Logic Analyzers HEWLETT PACKARD Evaluation Boards KEIL Software PHYTEC RIGEL HIGHTEC ertec pls Sockets / Adapters Yamaichi ET EMULATION TECHNOLOGY, INC. RTOS KEIL Software CMX Company HIGHTEC tecsi WindRiver Systems Simulators KEIL Software hitex TASKING KEIL Software Debuggers pls TASKING Flash Programmers ertec CEIBO hitex pls Development Tools 27

Applications for the C166 Family
Processor -System ROM / Flash CPU RAM Interrupt-System OSC. PEC WDT Ext. X-Bus USART GPTs CAPCOM Bus Control Periphrl. ADC Sync Communication PWM Peripheral-System PORTS Automotive Industrial Control Consumer Telecom/ Datacom EDP Engine Management Transmission Control ABS/ASK Active Suspension Robotics PLC’s Servo-Drives Motor Control Power-Inverters Machine-Tool Control (CNC) DVD / CD-ROM TV / Monitor VCR / Sat Receiver Set Top Box Games Video Surveillance Communication Boards (LAN) Modems PBX Mobile Communication Hard Disk Drives Tape Drives Printers Scanners Digital Copiers FAX Machines C166 Family 28

C166 Family-High Performance 16-Bit Microcontrollers

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C166 Family-High Performance 16-Bit Microcontrollers

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