1 Figure 9.1 2-to-1 Multiplexer and Switch Analog A multiplexer(MUX, or Data selector)Figure to-1 Multiplexer and Switch AnalogWhen A is 0, the switch to the upper position, then output Z=I 0When A is 1, the switch to the lower position, then output Z=I 1
2 Figure 9.2 Multiplexers 4-to-1 MUX, 8-to-1 MUX, and 2n-to-1 MUX Take 4-to-1 MUX, it needs 2-control input to select 4-data input.When AB is 00, then we Z=I0. when it is 01,10,11 is corresponding to I1,I2,I3.
3 Figure 9.3 Logic Diagram for 8-to-1 MUX The logic diagram for a 8-to-1 MUXFigure 9.3 Logic Diagram for 8-to-1 MUX
4 Figure 9.4 Quad Multiplexer Used to Select Data * Multiplexers are frequently used in digital system design to select the data whichis to be processed or stored .*How a quad MUX used to select one of two 4-bit data words…when A=0, X0, X1,X2,X3 is appear to Zo, Z1,Z2,Z3.Otherwise, A=1; Y0, Y1,Y2,Y3 is appear to Zo, Z1,Z2,Z3.“Bus”Several logic signals that perform a commonfunction may be grouped together to form a bus.
5 Figure 9.6 Gate Circuit with Added Buffer A simple buffer may be used to increase the driving capability of a gate output.Two or more gates outputs or other logic device directly connected to each other.When one gate has 0 output(low-voltage), another has 1(high-voltage), then theresulting output don’t clearly represented. Also damage to the gate can occurs.
6 Figure 9.7 Three-State Buffer A Three-state bufferFigure 9.7 Three-State BufferWhen B=1, the output C is equal to AWhen B=0, the output C acts like an open circuit (High-impedance, Hi-Z)
7 Figure 9.8 Four Kinds of Three-State Buffers Inverted input
8 Figure 9.9 Data Selection Using Three-State Buffers When select line B is 0, D= AThen B=1, D=C Therefore, D= B’A+ BCThis is logically equivalent to using a 2-to-1 MUX.
9 Figure 9.10 Circuit with two Three-State Buffers Three-state Buffer shows Hi-Z(open circuit), The possible output is as-below:
13 Figure 9.14 A 4-to-10 Line Decoder Decoder (A 4-to-10 line decoder)Figure 9.14 A 4-to-10 Line DecoderThis decoder has inverted outputs exactly oneof the output will be 0
14 Figure 9.15 Realization of a Multiple-Output Circuit Using a Decoder Decoder outputs are invertedFigure 9.15 Realization of a Multiple-Output Circuit Using a DecoderORing to the output,butfor the inverted decoder, the NAND gate used togenerate the function.
15 Figure 9.16 An 8-to-3 Priority Encoder Encoder (A encoder performs the inverse function of a decoder)Figure 9.16 An 8-to-3 Priority EncoderA 8x3 encoder
16 Priority Encoder (why we need this encoder ?) When more than one input can be 1 at the same time, the output may not the right.for example, a 8x3 encoder, when A3=1 and A4=1 at the same time, the output is(Y2, Y1, Y0)=(1,1,1). This is not the right output code.That is the reason why we need a Priority encoder.If we have y1=1, y4=1, y5=1 at the same time, based on the Priority encoder,the highest numbered input is determined. So y5=1, then output is (101)
17 Figure 9.17 An 8-Word X 4-Bit ROM Read-only Memories(ROM)Figure 9.17 An 8-Word X 4-Bit ROMEach output patterns is stored in the ROM is called a wordEach input combination serves as an address which can select one of the wordsstored in the memory.We defined a ROM (2n x m ROM), means an array of 2n words and each wordis m bits long.(word)
18 Figure 9.18 Read-Only Memory with n inputs and m Outputs A 2n x m ROMFigure 9.18 Read-Only Memory with n inputs and m Outputs
20 Figure 9.20 An 8-Word X 4-Bit ROM The internal structure of the 8-word x4 bit ROMFigure 9.20 An 8-Word X 4-Bit ROMThe memory array forms the 4 output functions by ORing together selected miniternsFrom previous truth table,ORing for F0
21 Figure 9.22 Hexadecimal-to-ASCII Code Converter Example: realize a code convertor by using ROMsFigure 9.22 Hexadecimal-to-ASCII Code ConverterConvert a 4-bit binary code to a hexadecimal, and output the 7-bits ASCII code.A4=A5, A6=A4’So we only need five ouputs4 address, creating 16 words; each words shows a 7-bit pattern!
22 Figure 9.23 ROM Realization of Code Converter ROM realization of code convertorFigure 9.23 ROM Realization of Code ConverterAn X indicates that the switching element is present and connected, and no XIndicate that the corresponding element is absent or not connected.
23 Read-only Memories(ROM) mask-programmable ROMs:a. The data is permanently stored.b. Accomplished by selectively including or omitting the switching elements.by using mask.c. Expensive, not economically feasible.Programmable ROMs(PROMs)Electrically erasable programmable ROMs(EEPROM):a. using special chage-stroge mechanism to enable or disable the switchingelements.b. Suitable for the developmental phase of a digital design.c. EEPROM can be erased and reprogrammed only a limited times( )EEPROM
35 Figure 9.32 Layout of a Typical FPGA Field-programmable gate array (FPGA)FPGA contain an array of logic cells(also called configurable logic blocks, CLB).The user can program the functions based on FPGA.Figure 9.32 Layout of a Typical FPGA
36 Figure 9.33 Simplified Configurable Logic Block (CLB) A simplified CLBFigure 9.33 Simplified Configurable Logic Block (CLB)This CLB shows output: X, Y, XQ, YQH1 can select the function generatorA 4-inputreprogrammable ROM
37 Figure 9.34 Implementation of a Lookup Table (LUT) The function generator (lookout table, LUT)Figure 9.34 Implementation of a Lookup Table (LUT)