1. 1 A 0.6V ULTRA LOW VOLTAGE OPERATIONAL AMPLIFIER 指導教授：林志明 所長 指導學生：賴信吉 Email ： s94662005@mail.ncue.edu.tw 彰師大 積體電路設計研究所

2. 2 Y. Tang and R. L. Geiger, “A 0.6V ULTRA LOW VOLTAGE OPERATIONAL AMPLIFIER,” IEEE International Symposium on Circuits and Systems, Phoenix, May 2002. Department of Electrical and Computer Engineering Iowa State University, Ames, IA 50011, U.S.A

3. 3 Outline Introduction Threshold voltage tuning Design of the low-voltage OP AMP and it’s supporting circuits Simulation results and comparison Conclusion

4. 4 Introduction 1.Low-voltage circuit design. 2.Voltage sources are added in series with the gates of the MOS transistors. 3.A standard 3.3V 0.35μ CMOS process without modifications. 4.Around threshold voltage level 5.20% power consumption of 3.3V counterpart.

5. 5 Threshold voltage tuning 1.Supply voltage limitation.→ Vth, V D SAT. 2.Threshold voltage around 0.7V. 3.The minimum supply voltage has been around 1.5V.

6. 6 § The basic concept of this low voltage technique is very simple. § It will have the same gm and go if biased at the same drain current level.

7. 7

8. 8 Design of the low-voltage OP AMP and it’s supporting circuits

9. 9 φ1 and φ2 are non-overlapping clocks. CMOS Rin ↑, switch leakage current ↓, soφ1 and φ2 can be low to reduce noise injection. NMOS

10. 10 Frequency divider ： D flip-flop, 64:1. 0.5MHz range 0.6V 01

11. 11 Bias voltage generator (simple self-biased circuit under 0.6V) 1.Roughly 0.2V below the threshold voltage. 2.Provide enough current so that during the charging of C 1.

12. 12 N-well CMOS process. Switches → NMOS bodies →ground Leakage < 1μA Issue……

13. 13 Simulation results and comparison To compare the performance of the low-voltage Op Amp (3.3V power supply, Vtn=0.55V, Vtp=0.6V, 0.35 μm CMOS process. )

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15. 15 Conclusion Simulation results show….. It maintains the key small signal parameters. Low voltage circuit exhibits a major decrease in power dissipation.