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An Ultra-Low-Voltage CMOS Mixer Using Switched-Transconductance Current-Reuse Dynamic-Threshold-Voltage Gain-Boosting Techniques Amir Hossein Masnadi and.

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Presentation on theme: "An Ultra-Low-Voltage CMOS Mixer Using Switched-Transconductance Current-Reuse Dynamic-Threshold-Voltage Gain-Boosting Techniques Amir Hossein Masnadi and."— Presentation transcript:

1 An Ultra-Low-Voltage CMOS Mixer Using Switched-Transconductance Current-Reuse Dynamic-Threshold-Voltage Gain-Boosting Techniques Amir Hossein Masnadi and Shahriar Mirabbasi IEEE NEWCAS, June 2012

2 Big Picture Above Picture : Smart Stents, SoC and MEMS lab, UBC Biomedical Application Low Power Wireless Communication Designing Building Blocks for Ultra-Low–Voltage/Power CMOS RF Front-End for applications such as:

3 Outline Overview of Conventional Active Mixers Overview of techniques – Stack Reduction, LO-Gm Separation – Current-Reuse – Dynamic Threshold Mixer Design – Gm-Stage - Double Balanced Current Reuse Gilbert Structure – LO -Stage - Switched Supply Voltage Post-Layout Simulation Results and Comparison Concluding remarks 3

4 Conventional Active Mixers Gilbert-Type Mixer (Current commutating) – 3 stacked transistors each transistor V DS is around V DD /3 Considering Vth is around 0.4 V, minimum supply voltage is around 1.2 V – To increase conversion gain (CG) one can increase load (CGαRL×) Penalty: more voltage drop across load trade-off between V DD and CG – Mixer core is always ON (For Biasing the transistors ) Even more challenging if IIP3 has to be improved Limitations for Supply-Voltage: Power Consumption issue: Challenge of biasing current source in saturation for low supply voltage (e.g. VDD < 1.5) Reduce the voltage drop across the Load Resistor to increase M1 drain Voltage

5 Supply Voltage (V) – Year ( ) Range of Threshold Voltage y = x Roughly Reduction of V/Year Bulk_Driven and Folded Methods Very Low CG (1

6 Mixer Power (mW)– Year ( ) y = x Roughly a reduction of 0.88 mW/Year (it is leveling off)

7 Design Bottlenecks Stacked Architectures : For decreasing Supply Voltage we should reduce Number of transistor Stacked stages, we have different methods, below we bring ONLY two of them : – Bulk-Driven Method Low Conversion Gain (Mostly below 10) Constant Biasing Current – Folded Gilbert Architecture Moderate Conversion Gain – Wide Band Constant Biasing Current Bulky Inductors Threshold Voltage : If decreases the headroom will increases, so it would be nice if we have lower threshold Voltage We can't find any significant publication for reducing threshold voltage in Mixers

8 Proposed Techniques for Ultra Low Voltage Mixer 1. Reducing Stacked Transistors by Switched Transconductance : – LO-Stage and G m -Stage can be separated by switching supply voltage of G m -Stage – Turn ON & Off Gm-Stage with LO Save Power Current Commutating Approach Gm ON/OFF Approach

9

10 Proposed Techniques for Ultra-Low-Voltage Mixer 2.Choosing Gm-Stage, Maximizing Conversion Gain and Linearity: Pick a proper G m -Stage for High Conversion Gain (High output G m ) and High Linearity Current-Reuse technique – Overal G m = g mn +g mp – Linearity will be improved Total G m =g mn +g mp Total G m =g mn Current-Reuse is similar to Push-Pull Buffer

11 Switching Stage We should implement a switch between V DD and GND – Different Options : Simple Digital Inverter High-speed comparator (compare LO with GND, requires low LO power) Inverter with Dynamic Threshold-Voltage: Reduce V TH of NMOS transistors by connecting inverter output to body of NMOS (DTMOS) Output voltage of the inverter with C L= 1pF, P LO = 8 dBm, 2.45 GHz LO signal and DC value of LO is 0.3 V, (a) with dynamic threshold (DTMOS) inverter (b) without DTMOS..

12 Proposed Building Block For ULV Mixer

13 Proposed Double-Balanced Design

14 Post-Layout Simulation Results Case 1 : Sub Threshold Case 2 : Sub Threshold Case 3 : Super Threshold Case 4 : Super Threshold Case 5 : Super Threshold V DD (V) V BN (V) V BP (V) P LO (dBm) NF (dB) CG (dB) IIP3 (dBm) P DC (mW) IBM0.13-µm CMOS V TH 0.42 V

15 Effect of Dynamic Threshold Technique

16 Conversion Gain at Different Supply Voltages

17 ParametersThis Work * JSSCRFIC MTT LO-Gm ArchitectureSeparated StackedFolded LO-Gm Separation Method DTMOS Inverter Conventional Inverter N/A Gm-Stage Current Reuse NMOS Curren t Reuse NMOS RF (GHz) IF (MHz) P LO (dBm) V DD (V) 0.35 Subthreshold Subthresho ld P DC (mW) NF (dB) IIP3(dBm) Conversion Gain (dB) CMOS Technology (µm) FOM 1 / FOM / / / / / / /21.31

18 Concluding Remarks TSMC 90nm Process Mixer Core Resonator Buffer Active Balun RF LO IF+ IF- Techniques to improve mixer performance: Reduce stacked levels For Gm-Stage, try to choose blocks with higher output Gm and Linearity Reduce V TH by body effect (Dynamic Threshold Technique), Both for Gm-Stage and LO-Stage, so we can use it for increasing headroom an Turn-off circuit when you dont want to use it to save power Resonator V DD (V)0.3 P LO (dBm)-8.4 CG (dB)27-15 Frequenc y DC-12GHz P DC (mW)0.09 mWatt

19 Acknowledgments 1.NSERC 2.CMC Microsystems IBM TSMC And thank you for listening! 19

20 R EFERENCES E.A.M. K LUMPERINK, S.M. L OUWSMA, G.J.M. W IENK, AND B. N AUTA, A CMOS SWITCHED TRANSCONDUCTOR MIXER, IEEE J OURNAL OF S OLID -S TATE C IRCUITS, ­­­ VOL.39, NO.8, PP , A UG Hanil Lee; Mohammadi, S., A 500μW 2.4GHz CMOS Subthreshold Mixer for Ultra Low Power Applications, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp , 3-5 June Kihwa Choi; Dong Hun Shin; Yue, C.P., A 1.2-V, 5.8-mW, Ultra-Wideband Folded Mixer in 0.13-μm CMOS, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp , 3-5 June Assaderaghi, F.; Sinitsky, D.; Parke, S.A.; Bokor, J.; Ko, P.K.; Chenming Hu; "Dynamic threshold- voltage MOSFET (DTMOS) for ultra-low voltage VLSI," Electron Devices, IEEE Transactions on, vol.44, no.3, pp , Mar V. Vidojkovic, et al., A Low-Voltage Folded-Switching Mixer in 0.18-um CMOS, IEEE J. Solid-State Circuits, vol. 40, pp , June S. He and C.E. Saavedra, An Ultra-Low-Voltage and Low-Power 2 Subharmonic Downconverter Mixer, IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 2, pp , Feb M. Huang, et al., "A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low-Voltage Applications," IEEE Trans. Microwave Theory Tech., vol. 54, no. 2, pp , Feb


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