1. Dual Core System-on-Chip Design to Support Inter- Satellite Communications Liza Rodriguez Aurelio Morales EEL 6935 - Embedded Systems Dept. of Electrical and Computer Engineering University of Florida

2. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 2 of 30 Outline Introduction Introduction Picosatellite Demostrator Design Picosatellite Demostrator Design Dual Core Processor Design Dual Core Processor Design Dual Core Processor Implementation Dual Core Processor Implementation Network Topology Reconfiguration Network Topology Reconfiguration Conclusions Conclusions

3. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 3 of 30 Outline Introduction Introduction Picosatellite Demonstrator Design Picosatellite Demonstrator Design Dual Core Processor Design Dual Core Processor Design Dual Core Processor Implementation Dual Core Processor Implementation Network Topology Reconfiguration Network Topology Reconfiguration Conclusions Conclusions

4. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 4 of 30 Satellites that provide multi-point sensing Low cost, redundancy, flexibility Types of DSS: Formation Flying: strict formation Clustering Mission: satellites are loosely coupled around each other Virtual Satellite Mission (fractioned mission): a satellite has its subsystems divided onto multiple crafts (computing, imaging, etc.) Distributed Satellite System (DSS) Introduction

5. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 5 of 30 Introduction DSS in Low Earth Orbit (LEO) Small satellites deployed at the same time in multiple orbits Use for disaster monitoring prevention Ad-hoc network for multipoint sensing like WSN Challenges: Attitude and orbit control, intersatellite links, on- board computing Deal with perturbations: Earth’s geophysical forces, solar radiation Network connectivity and topology over time

6. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 6 of 30 Distributed Computing Requirements Introduction Node LevelNode Level At Individual satellite level Store and forward data using the network: High priority apps using Client/Server. Payload data through the network such imaging data Low priority apps using Peer-to-Peer telemetry. Location and velocity changes, “byte” size payload data (GPS) Network LevelNetwork Level Applied to multiple satellites Provide adaptable and redundant ground-link communication schemes, main “sink” to ground React proactively and reactively to their environment

7. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 7 of 30 IntroductionMotivation Meet requirements for processing and network capabilities in “cluster” of satellites in the presence of space disturbances Proposal Dual core System-on-Chip design using a general purpose soft-core processor and a specific core for real-time applications, such as agents

8. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 8 of 30 Agenda Introduction Introduction Picosatellite Demonstrator Design Picosatellite Demonstrator Design Dual Core Processor Design Dual Core Processor Design Dual Core Processor Implementation Dual Core Processor Implementation Network Topology Reconfiguration Network Topology Reconfiguration Conclusions Conclusions

9. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 9 of 30 Use of embedded hardware technology Standard picosatellite platform CubeSat For fast prototype, COTS components/boards: Flight OBC and satellite chassis from Pumpkin Power module from Clyde-Space SGR-05 GPS module from SSTL MHX transceiver from Microhard Systems PF5100 Virtex-4 FPGA FX60 Board for SoC IEEE 802.11 PC/104 Board from Elcard Picosatellite Demonstrator Design Prototype

10. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 10 of 30 Prototype CubeSat Platform with Flight Module, IEEE 802.11, FPGA and development boards

11. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 11 of 30 Prototype MHX 900 MHz TransceiverPF5100 Board with Virtex-4 FPGA SGR-05U – Space GPS Receiver Flight module and satellite Chassis Power Module IEEE 802.11 Board

12. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 12 of 30 1999, CalPoly and Stanford University developed specs to help universities worldwide perform space exploration. Very small satellite Use COTS components 10x10x10 cm structure Weight of 1 Kg Also in 2U and 3U sizes CubeSat

13. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 13 of 30 Demonstrator Satellite Architecture FPGA board, IEEE 802.11 board, camera as payloads. OBCArchitecture controlled by the Flight On-Board Computer (FM430 OBC) SoC to act as HW/SW mediator for: Hard and soft resets Sleep mode SoC also used as interface between various buses Demonstrator Satellite Architecture

14. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 14 of 30 Agenda Introduction Introduction Picosatellite Demonstrator Design Picosatellite Demonstrator Design Dual Core Processor Design Dual Core Processor Design Dual Core Processor Implementation Dual Core Processor Implementation Network Topology Reconfiguration Network Topology Reconfiguration Conclusions Conclusions

15. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 15 of 30 Dual Core Processor Design LEON3 Processor Synthesisable VHDL model of 32-bit processor compliant with SPARC V8 architecture Suitable for SoC designs JOP Processor JOPJava Optimized Processor Enables real-time Java functionality Smallest and fastest Java core

16. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 16 of 30 LEON3 Processor Dual Core Processor Design

17. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 17 of 30 Dual Core Processor Design LEON3 core and JOP core in a FPGA FPGA SoC design AMBA AMBA = Advanced Microcontroller Bus Architecture APB APB = Advanced Peripheral Bus

18. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 18 of 30 Design Considerations Dual Core Processor Design Memory sharing system between LEON3 and JOP for access to external RAM Cache between cores must maintain coherency Reconfiguration in cases of single event upsets (SEUs) or single event latch-ups (SELs)

19. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 19 of 30 low memory footprintSystem must have low memory footprint, including OS and network stack real-timeSystem must be real-time CLDCpjavaCLDC and pjava are designed for devices with intermittent network connection, slow processors, limited memory (e.g. mobile phones, PDAs), making them ideal for JOP core Memory Footprint Comparison CLDC CLDC = Connection Limited Device Configuration pjava = PersonalJava JADE JADE= Java Agent DEvelopment Framework LEAP LEAP =Light Extensible Agent Platform CORBA CORBA = Common Object Request Broker Architecture Multi-layer software design Dual Core Processor Design

20. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 20 of 30 Hardware and software layer design Dual Core Processor Design LEON3 and JOP in FPGA: Reduce memory footprint Increase FPGA utilization Enable Java apps, such as Agents, for real-time apps RTEMS RTEMS = Real-Time Exceutive for Multiprocessor Systems

21. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 21 of 30 System-on-Chip Block Diagram Detailed System-on-Chip design Dual Core Processor Design

22. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 22 of 30 Outline Introduction Introduction Picosatellite Demonstrator Design Picosatellite Demonstrator Design Dual Core Processor Design Dual Core Processor Design Dual Core Processor Implementation Dual Core Processor Implementation Network Topology Reconfiguration Network Topology Reconfiguration Conclusions Conclusions

23. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 23 of 30 Max Frequency of 37.398 MHz WCET found between: LEON3 and AMBA memory controller LEON3 and JOP AHB Master JOP cache and JOP address bus Speed optimization is needed to satisfy IEEE 802.11 MAC. Trade-off between area and speed Dual Core Processor Implementation Timing Results

24. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 24 of 30 Dual Core Processor Implementation On-chip or off-chip memory? Speed and power requirements On-chip: fast but increase power consumption and area Power consumption of SoC design: 2.33W (1.76W in memory interfacing), using XPower from Xilinx Memory Trade-off Resource Utilization

25. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 25 of 30 Outline Introduction Introduction Picosatellite Demonstrator Design Picosatellite Demonstrator Design Dual Core Processor Design Dual Core Processor Design Dual Core Processor Implementation Dual Core Processor Implementation Network Topology Reconfiguration Network Topology Reconfiguration Conclusions Conclusions

26. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 26 of 30 Procedure Network Topology Reconfiguration HW & SW are discovered Network topology can be reconfigured Stage 1: Startup FPGA Bus System & LEON3 LEON3 started, id and starting tasks discovered Stage 2: Startup JOP & JADE-LEAP Start Java application with argument passing to main host and services required Stage 3: Network Topology Refresh Initialize, check or change the network topology

27. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 27 of 30 Outline Introduction Introduction Picosatellite Demonstrator Design Picosatellite Demonstrator Design Dual Core Processor Design Dual Core Processor Design Dual Core Processor Implementation Dual Core Processor Implementation Network Topology Reconfiguration Network Topology Reconfiguration Conclusions Conclusions

28. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 28 of 30 A COTS solution for picosatellite including a SoC design that meets CubeSat platform was introduced. LEON3 IP and JOP IP cores were used to meet strict requirement of low memory footprint, Java functionality and real-time operation An Java agent software was proposed to support inter-satellite communication based on IEEE 802.11 wireless connectivity Conclusions

29. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 29 of 30 References http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4584273 http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4584273http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4584273 http://www.cubesat.org/ http://www.cubesat.org/http://www.cubesat.org/ http://en.wikipedia.org/wiki/CubeSat http://en.wikipedia.org/wiki/CubeSathttp://en.wikipedia.org/wiki/CubeSat http://www.cubesatkit.com/index.html http://www.cubesatkit.com/index.htmlhttp://www.cubesatkit.com/index.html http://www.derivation.com/products/pf5100.html http://www.derivation.com/products/pf5100.htmlhttp://www.derivation.com/products/pf5100.html http://www.clyde-space.com/products/electrical_power_systems/cubesat_power http://www.clyde-space.com/products/electrical_power_systems/cubesat_powerhttp://www.clyde-space.com/products/electrical_power_systems/cubesat_power http://www.sstl.co.uk/assets/Downloads/SGR-05U%20v1_13.pdf http://www.sstl.co.uk/assets/Downloads/SGR-05U%20v1_13.pdfhttp://www.sstl.co.uk/assets/Downloads/SGR-05U%20v1_13.pdf http://www.data-connect.com/Microhard_MHX-910.htm http://www.data-connect.com/Microhard_MHX-910.htmhttp://www.data-connect.com/Microhard_MHX-910.htm http://www.gaisler.com/doc/leon3_product_sheet.pdf http://www.gaisler.com/doc/leon3_product_sheet.pdfhttp://www.gaisler.com/doc/leon3_product_sheet.pdf

30. EEL 6935 Dual Core SoC Design to Support Inter-Satellite Communications 30 of 30 Questions?